Abstract: A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.

Abstract: Memory graphics processing units (GPUs) are provided. In one aspect, a GPU for massive parallel processing of at least part of an image includes a plurality of pixel processing cores, each of the pixel processing cores configured to process a pixel of the image, and each of the pixel processing cores comprising a plurality of bit processing cores each configured to process a bit of the image and a plurality of address lines configured to provide access to the bit processing cores. The pixel processing cores are configured to process pixels of the image in parallel.

Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.

Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal. A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.

Abstract: Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal. A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.

Abstract: A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.

Abstract: A circuit utilizing memcapacitive elements for mixed memory storage and polymorphic computing is introduced. The circuit includes a plurality of memory cells each selectively or fixedly connected to a word line, bit line and dual bit line. Each memory cell includes a memcapacitive element. Voltage pulse generators can selectively applying voltage pulses to the memory cells. A method for mixed memory storage and polymorphic computing in at least two memory cells is provided. Data is stored by selectively applying voltage pulses to an individual memory cell to set an internal charge level of the memcapacitive element. Logic functions are conducted by applying voltage pulses having independent amplitudes to at least two memory cells to achieve internal charges in the memcapacitive elements of the cells to store an output bit according to a logic map that depends upon applied independent voltage pulse amplitudes.