Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load through a power MOS, being an improvement of the limiting circuitry which uses an equalizing capacitor. The addition of circuitry with a one-way current flow between a terminal of the equalizing capacitor and the gate terminal of the power MOS is effective to lower the voltage across the capacitor and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuitry which limits current flow to one direction may include a second MOS of the same type as the power MOS. In this way, any deviations of the power MOS from its designed operation, e.g. due to its manufacturing process variation and thermal drift phenomena, can also be compensated.