Patents by Inventor Fabio Marchisi
Fabio Marchisi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935818Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.Type: GrantFiled: May 24, 2021Date of Patent: March 19, 2024Assignee: STMICROELECTRONICS S.r.l.Inventor: Fabio Marchisi
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Publication number: 20230245994Abstract: A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.Type: ApplicationFiled: January 27, 2023Publication date: August 3, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mauro MAZZOLA, Fabio MARCHISI
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Publication number: 20230245955Abstract: A semiconductor device includes an electrically conductive clip arranged in a bridge-like position between a semiconductor integrated circuit chip and an electrically conductive pad of a leadframe. The electrically conductive clip is soldered to the semiconductor integrated circuit chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor integrated circuit chip and the electrically conductive pad. Prior to soldering, the clip is immobilized in the desired bridge-like position via one of welding (such as laser welding) or gluing at dedicated immobilization areas.Type: ApplicationFiled: January 26, 2023Publication date: August 3, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mauro MAZZOLA, Fabio MARCHISI
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Publication number: 20220059369Abstract: A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.Type: ApplicationFiled: August 20, 2021Publication date: February 24, 2022Applicant: STMicroelectronics S.r.l.Inventors: Marco ROVITTO, Pierangelo MAGNI, Fabio MARCHISI
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Publication number: 20210305134Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.Type: ApplicationFiled: May 24, 2021Publication date: September 30, 2021Applicant: STMICROELECTRONICS S.R.L.Inventor: Fabio MARCHISI
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Patent number: 11018078Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.Type: GrantFiled: July 10, 2018Date of Patent: May 25, 2021Assignee: STMICROELECTRONICS S.r.l.Inventor: Fabio Marchisi
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Patent number: 10535535Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.Type: GrantFiled: June 27, 2018Date of Patent: January 14, 2020Assignee: STMICROELECTRONICS S.R.L.Inventor: Fabio Marchisi
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Publication number: 20190181076Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.Type: ApplicationFiled: December 7, 2018Publication date: June 13, 2019Inventors: Dario VITELLO, Fabio MARCHISI, Alberto ARRIGONI, Federico FREGO, Federico Giovanni ZIGLIOLI, Paolo CREMA
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Publication number: 20190043787Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.Type: ApplicationFiled: July 10, 2018Publication date: February 7, 2019Inventor: Fabio MARCHISI
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Publication number: 20190006191Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.Type: ApplicationFiled: June 27, 2018Publication date: January 3, 2019Inventor: Fabio MARCHISI
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Patent number: 10074596Abstract: An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of electrically conductive material. The lead frame is produced by an additive process of conductive material, e.g., by 3D printing, by forming a three-dimensional structure of leads having overlapping surfaces with a gap therebetween.Type: GrantFiled: December 15, 2015Date of Patent: September 11, 2018Assignee: STMICROELECTRONICS S.R.L.Inventor: Fabio Marchisi
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Patent number: 9997438Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.Type: GrantFiled: June 23, 2017Date of Patent: June 12, 2018Assignee: STMICROELECTRONICS S.R.L.Inventor: Fabio Marchisi
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Publication number: 20170294370Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.Type: ApplicationFiled: June 23, 2017Publication date: October 12, 2017Inventor: Fabio Marchisi
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Patent number: 9640464Abstract: A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.Type: GrantFiled: August 12, 2016Date of Patent: May 2, 2017Assignee: STMicroelectronics S.r.l.Inventor: Fabio Marchisi
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Publication number: 20160351477Abstract: A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.Type: ApplicationFiled: August 12, 2016Publication date: December 1, 2016Applicant: STMicroelectronics S.r.l.Inventor: Fabio Marchisi
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Publication number: 20160315035Abstract: An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of electrically conductive material. The lead frame is produced by an additive process of conductive material, e.g., by 3D printing, by forming a three-dimensional structure of leads having overlapping surfaces with a gap therebetween.Type: ApplicationFiled: December 15, 2015Publication date: October 27, 2016Inventor: Fabio MARCHISI
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Publication number: 20160172275Abstract: A surface-mount electronic device includes a body of semiconductor material, a lead frame, which forms a plurality of contact terminals, and a package dielectric region, which overlies the semiconductor body. Each contact terminal includes an inner portion that is overlaid by the package dielectric region and an outer portion, which projects laterally beyond the package dielectric region and is delimited by a first lateral surface. The device further includes, for each contact terminal, an anti-oxidation layer, which is disposed on the corresponding first lateral surface.Type: ApplicationFiled: August 31, 2015Publication date: June 16, 2016Applicant: STMICROELECTRONICS S.R.L.Inventor: Fabio Marchisi
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Publication number: 20080012102Abstract: A semiconductor-integrated electronic device comprises a body and a plurality of leads, adjacent and in spaced relationship to each other, projecting from at least one edge of the body. The device further comprises a spacer device which comprises a plurality of insulating teeth interposed between the plurality of leads, so as to form an insulating barrier between adjacent leads of the plurality of leads.Type: ApplicationFiled: July 6, 2007Publication date: January 17, 2008Applicant: STMicroelectronics S.r.l.Inventors: Fabio Marchisi, Giuliano Babulano