Abstract: A method of operating a radio transmitter configured to transmit at least one sequence of logic values by transmitting transmission signals selected in a constellation diagram having a certain cardinality comprises selecting said transmission signals out of a first subset of transmission signals in said constellation diagram, said first subset comprising a first number of transmission signals, and a second subset of transmission signals in said constellation diagram, said second subset comprising a second number of transmission signals, wherein. The transmission signals in the second subset of transmission signals have an energy higher than the transmission signals in the first subset of transmission signals. The sum of said first number of transmission signals and said second number of transmission signals is less than said cardinality.

Abstract: A method of operating a radio transmitter configured to transmit at least one sequence of logic values by transmitting transmission signals selected in a constellation diagram having a certain cardinality comprises selecting said transmission signals out of a first subset of transmission signals in said constellation diagram, said first subset comprising a first number of transmission signals, and a second subset of transmission signals in said constellation diagram, said second subset comprising a second number of transmission signals, wherein. The transmission signals in the second subset of transmission signals have an energy higher than the transmission signals in the first subset of transmission signals. The sum of said first number of transmission signals and said second number of transmission signals is less than said cardinality.

Abstract: A method and system for decoding signals includes a transmitter configured for transmitting signals encoded with a mapping, with different and separable configurations in a real part and an imaginary part of the signal. The signals may be encoded according to a Gray or QAM mapping, and may be transmitted on a selective MIMO channel and/or multiplexed with an OFDM technique. The corresponding receiver is configured for decoding the real part and the imaginary part of the signals separately, and may include a filter for subjecting the encoded signals to a Wiener filtering and a MMSE detector for minimizing the mean-square error between the encoded signals and the result of the Wiener filtering. The receiver may also include a soft decoder for performing a soft estimation of the signals and cancelling, using the results of the soft estimation, an interference produced on the signals.

Abstract: A wireless CDMA communication system receiver receives a stream of chips generated by spreading data symbols formed by grouping bits of information at a wireless CDMA communication transmitter which are broadcast at a certain chip-rate. The received chips are de-spread and symbols pertaining to respective users are reconstructed. The stream of chips are formatted into blocks of chips, and an iterative block decision feedback equalization is performed in a frequency domain at the chip-rate of the broadcast stream of chips to remove inter-symbol interference by defining a transfer function. The chips generated are interleaved by spreading each data symbol being transmitted before broadcasting the stream of interleaved chips in distinct blocks of chips.

Abstract: A method for designing a new prunable S-random interleaver class to be used as a constituent part of turbo codes. With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized “ad hoc” S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i e., one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

Abstract: A system for the transmission of signals comprises a transmitter configured for transmitting signals xt, encoded with a mapping, with different and separable configurations in the real part and the imaginary part of the signal. These may be, for example, signals xt encoded according to a Gray mapping, signals xt encoded with two QAM mappings, encoded signals xt transmitted on a selective Multiple-Input/Multiple-Output (MIMO) channel and/or encoded signals xt multiplexed with an Orthogonal-Frequency-Division-Multiplexing (OFDM) technique. The corresponding receiver is configured for decoding in a distinct way the real part R(xt) and the imaginary part I(xt) of said signals, and typically comprises a filter for subjecting said encoded signals xt to a Wiener filtering {circumflex over (x)}t, and a Minimum-Mean-Square-Error (MMSE) detector configured for minimizing the mean-square error between said encoded signals xt and the result of said Wiener filtering {circumflex over (x)}t.

Abstract: A method for canceling interference at a wireless code division multiple access (CDMA) communication receiver is provided. The wireless CDMA communication system receiver receives a stream of chips generated by spreading data symbols formed by grouping bits of information at a wireless CDMA communication transmitter which are broadcast at a certain chip-rate. The received chips are de-spread and symbols pertaining to respective users are reconstructed. The method includes formatting the stream of chips into blocks of chips, and performing an iterative block decision feedback equalization in a frequency domain at the chip-rate of the broadcast stream of chips to remove inter-symbol interference by defining a transfer function. The transfer function is defined based upon iteration cycles as a function of data detected in a preceding iteration cycle. The chips generated are interleaved by spreading each data symbol being transmitted before broadcasting the stream of interleaved chips in distinct blocks of chips.

Abstract: An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by means of a two-dimensional modulation scheme such as M-PSK or M-QAM. The corresponding decoding process involves an iterative decoding algorithm based on cascaded logarithmic soft-input soft-output processing steps.

Abstract: A method for designing a new prunable S-random interleaver class to be used as a constituent part of turbo codes. With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized “ad hoc” S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i e., one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

Abstract: An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by means of a two-dimensional modulation scheme such as M-PSK or M-QAM. The corresponding decoding process involves an iterative decoding algorithm based on cascaded logarithmic soft-input soft-output processing steps.

Abstract: A sigma-delta modulator of second or higher order includes two or more integrating stages, and a comparator connected in cascade to the integration stages. A signal having a logic level +1 is generated when an input signal to the sigma-delta modulator is positive, and a signal having a logic value −1 is generated when the input signal is negative. Regardless of its absolute value, a feedback line includes a low-pass filter and an adder circuit for adding a feedback signal. The signal output by the last of the integrating stages is filtered by the low-pass filter. The sigma-delta modulator further includes a second comparator having an input connected in common to the input of the first comparator and an output connected to an input of the low-pass filter. The second comparator outputs a logic signal having a positive value when the input signal is positive, and outputs a logic signal having a negative value when the input signal is negative.