Patents by Inventor Fabio Pellizzer

Fabio Pellizzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142838
    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 1, 2025
    Inventors: Srivatsan Venkatesan, Fabio Pellizzer
  • Patent number: 12283316
    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: April 22, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Fabio Pellizzer, Mattia Robustelli, Alessandro Sebastiani
  • Publication number: 20250120098
    Abstract: Methods for, apparatuses with, and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.
    Type: Application
    Filed: October 23, 2024
    Publication date: April 10, 2025
    Inventors: Lorenzo Fratin, Paolo Fantini, Fabio Pellizzer
  • Publication number: 20250107105
    Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
    Type: Application
    Filed: December 13, 2024
    Publication date: March 27, 2025
    Inventors: Paolo Fantini, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 12236999
    Abstract: Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Paolo Fantini
  • Publication number: 20250061943
    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 20, 2025
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
  • Patent number: 12219883
    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Stephen W. Russell, Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 12219782
    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Srivatsan Venkatesan, Fabio Pellizzer
  • Patent number: 12219784
    Abstract: Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Paolo Fantini, Fabio Pellizzer
  • Publication number: 20250037761
    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 12176042
    Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Fabio Pellizzer, Innocenzo Tortorelli
  • Patent number: 12178054
    Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 12171105
    Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: December 17, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Paolo Fantini
  • Publication number: 20240404606
    Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.
    Type: Application
    Filed: August 13, 2024
    Publication date: December 5, 2024
    Inventors: Karthik Sarpatwari, Fabio Pellizzer, Nevil N. Gajera
  • Patent number: 12148467
    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 12150317
    Abstract: Methods for, apparatuses with, and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a dielectric material positioned between the first plurality and the second plurality of word line plates, the dielectric material extending in a serpentine shape over the substrate; a plurality of pillars formed over and coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess between a respective word line plate and a respective pillar, wherein the recess is of an arch-shape, and the chalcogenide material in the recess contacts the respective word line plate.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Paolo Fantini, Fabio Pellizzer
  • Publication number: 20240321347
    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
    Type: Application
    Filed: April 23, 2024
    Publication date: September 26, 2024
    Inventors: Mattia Robustelli, Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano
  • Patent number: 12100447
    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
  • Publication number: 20240312521
    Abstract: Methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. Manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. For example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. A set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 19, 2024
    Inventors: Fabio Pellizzer, Russell L. Meyer, Stephen W. Russell, Lorenzo Fratin
  • Publication number: 20240312518
    Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.
    Type: Application
    Filed: February 23, 2024
    Publication date: September 19, 2024
    Inventors: Innocenzo Tortorelli, Hari Giduturi, Fabio Pellizzer