Abstract: Methods, systems, and devices for charge trapping flash NOR memory in memory systems are described. A memory system may include processing circuitry configured to perform one or more operations, a not-or (NOR) memory device coupled with the processing circuitry via a first interface, and a volatile memory device coupled with the NOR memory device via a second interface and the processing circuitry. Accordingly, the NOR memory device may be configured to provide first data, such as one or more model parameters for an artificial intelligence model, to the processing circuitry via the first interface as part of performing a first operation of the one or more operations. The volatile memory device may be configured to communicate second data, such as updated model parameters, with the NOR memory device via the second interface and the processing circuitry as part of performing a second operation of the one or more operations.

Abstract: Methods, systems, and devices for manufacturing a charge trap memory system are described. The method of manufacturing may include forming first pillars that extend through a stack of layers of the memory system, forming first cavities that extend though the stack of layers and are each positioned between respective pairs of the first pillars, forming piers in the first cavities, forming second cavities that extends through the stack of layers by removing some of the material of the first pillars, and forming second pillars in the second cavities.

Abstract: Methods, systems, and devices for ferroelectric NOR memory architectures are described. A memory device may include a first pillar, a second pillar, and a third pillar positioned between the first and second pillars. The memory device may include multiple first memory cells positioned between a respective first word line and a first semiconductor material at a first side of the third pillar and multiple second memory cells positioned between a respective second word line and the first semiconductor material at a second side of the third pillar. The memory device may include multiple first portions and second portions of a second semiconductor material, where each first portion couples a respective first memory cell and a respective second memory cell to the first pillar, and where each second portion couples a respective first memory cell and a respective second memory cell to the second pillar.

Abstract: Methods, systems, and devices for ferroelectric NOR memory architectures are described. The ferroelectric NOR memory architecture may include a first pillar, a second pillar, and a third pillar positioned between the first and second pillars. The memory device may include multiple first memory cells positioned between a respective first word line and a first semiconductor material at a first side of the third pillar and multiple second memory cells positioned between a respective second word line and the first semiconductor material at a second side of the third pillar. The memory device may include multiple first portions and second portions of a second semiconductor material, where each first portion couples a respective first memory cell and a respective second memory cell to the first pillar, and where each second portion couples a respective first memory cell and a respective second memory cell to the second pillar.

Abstract: Methods, systems, and devices for ferroelectric NOR memory architectures are described. The ferroelectric NOR memory architecture may include a first pillar, a second pillar, and a third pillar positioned between the first and second pillars. The memory device may include multiple first memory cells positioned between a respective first word line and a first semiconductor material at a first side of the third pillar and multiple second memory cells positioned between a respective second word line and the first semiconductor material at a second side of the third pillar. The memory device may include multiple first portions and second portions of a second semiconductor material, where each first portion couples a respective first memory cell and a respective second memory cell to the first pillar, and where each second portion couples a respective first memory cell and a respective second memory cell to the second pillar.

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

Abstract: Methods, systems, and devices for trench and pier architectures for three-dimensional memory arrays are described. A semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed to form voids, the pier structures may provide mechanical support of the cross-sectional pattern of the remaining material. In some examples, such pier structures may be formed within or along trenches or other features aligned along a direction of a memory array, which may provide a degree of self-alignment for subsequent operations.

Abstract: Memory devices, such as three-dimensional cross-point memory devices, and methods of manufacturing such devices are addressed. Multiple methods of manufacturing such memory devices are described to provide improved protection of replacement gate structures, such as word lines and in some examples, word line liners. These include processing flows which form one or more additional barrier structures between structures subject to at least partial removal during the processing flow; wherein some portion of the additional barrier structure(s) will remain at the end of manufacturing.

Abstract: Methods, systems, and devices for memory cell formation in pier and pillar architectures are described. A stack of materials including alternating layers of nitride and oxide may be formed, and a plurality of columns of a third material may be formed in the stack. The third material may be recessed (e.g., laterally) filled with at least an electrode liner and a metal material. Portions of the nitride material and an oxide liner that are adjacent to the third material may be removed, and a second electrode liner may be formed (e.g., in the regions from which the nitride material and oxide liner were removed). Memory cells may be formed after removing the portion of the nitride material and oxide liner such that the cells are in contact with the second electrode liner.

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.

Abstract: Methods, systems, and devices for charge trapping NOR Flash memory architectures are described. A memory device may include a pier positioned between a first pillar and a second pillar, where the pier includes multiple first memory cells at a first end of the pier and multiple second memory cells at a second end of the pier. The first pillar may be coupled with the pier via multiple first conductive paths and the second pillar may be coupled with the pier via multiple second conductive paths, where each first conductive path couples a respective first and second memory cell with the first pillar and each second conductive path couples a respective first and second memory cell to the second pillar. The memory device may include multiple first word lines each coupled with a respective first memory cell and include multiple second word lines each coupled with a respective second memory cell.

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Abstract: Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

Abstract: Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.

Abstract: Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.

Abstract: Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.

Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.