Abstract: A memory integrated circuit component comprises: a memory; addressing circuitry for the memory; and, power switch circuit, programmable to either: (a) electrically couple or decouple the addressing circuitry and a power supply selectively in accordance with an enable signal; or, (b) maintain the addressing circuitry electrically coupled to the power supply independent of the enable signal.With such arrangement, an integrated circuit component manufacturer avoids having to produce two separate types of non-volatile integrated circuit memories (i.e., a power switched component and a non-power switched component), but rather such manufacturer is able to fabricate a common non-volatile integrated circuit memory component which may be programmed after fabrication by either the user or the manufacturer as either a non-power switched memory component or a power switched memory component.

Abstract: An integrated circuit memory is disclosed having a power switch circuit which, in response to an enable signal, initially addresses a plurality of rows of memory elements during an initial pre-enable condition and which subsequently places the memory in the full enable condition to allow the address signal to address only a selected one of the plurality of memory elements. During a standby mode the rows of conductors coupled to the rows of memory elements are at a relatively "high" voltage potential charging the large capacitance between the rows of conductors and a grounded substrate on which such conductors are formed. To address a particular row conductor and hence the memory elements coupled thereto during the enable mode, such row conductor must be coupled to ground potential.

Abstract: A memory is provided having a plurality of addressable memory elements, each one thereof having a first programmable device electrically coupled to a second programmable device, the first programmable device having a normally low resistance characteristic which, when programmed, is changed to a relatively high resistance characteristic, and the second programmable device having a normally high resistance characteristic which, when programmed, is changed to a relatively low resistance characteristic. The first programmable device and second programmable device are serially connected to provide an array of memory elements having a relatively high resistance characteristic in an initial, unprogrammed condition. The memory is first programmed by changing the resistance characteristic of selected ones of the second programmable elements. If it is desired to reprogram the memory, the resistance characteristic of selected ones of the first programmable elements are changed.

Abstract: A programmable read-only memory (PROM) circuit is provided wherein each one of a plurality of fusible links is coupled between a different row and column conductor of a matrix of row and column conductors and wherein each one of the row conductors is coupled to a corresponding one of a plurality of row driver circuits, each one having an output transistor connected to the corresponding one of the row conductors. Switch means are provided for feeding a first level of base current to the output transistors during the programming mode and for feeding a second, lower level of base current to such output transistors during the read mode.