Patents by Inventor Fabrice Devaux

Fabrice Devaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210398584
    Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
    Type: Application
    Filed: November 13, 2020
    Publication date: December 23, 2021
    Inventors: Fabrice DEVAUX, Renaud AYRIGNAC
  • Publication number: 20210349826
    Abstract: A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.
    Type: Application
    Filed: September 6, 2017
    Publication date: November 11, 2021
    Inventors: Jean-François ROY, Fabrice DEVAUX
  • Patent number: 11049544
    Abstract: A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: June 29, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Gilles Hamou
  • Publication number: 20210012832
    Abstract: A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.
    Type: Application
    Filed: May 18, 2018
    Publication date: January 14, 2021
    Inventors: Fabrice DEVAUX, Gilles HAMOU
  • Patent number: 10884657
    Abstract: A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 5, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10885966
    Abstract: A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Renaud Ayrignac
  • Patent number: 10817288
    Abstract: A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 27, 2020
    Assignee: UPMEM
    Inventors: Fabrice Devaux, David Furodet
  • Patent number: 10324870
    Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 18, 2019
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Publication number: 20190050223
    Abstract: A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.
    Type: Application
    Filed: January 19, 2017
    Publication date: February 14, 2019
    Inventors: Fabrice Devaux, David Furodet
  • Publication number: 20180260161
    Abstract: A computer device comprises a first processing device; a plurality of memory circuits, a first one of which comprises one or more other processing devices; a data bus coupling the first processing device to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processing device and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting the first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.
    Type: Application
    Filed: September 27, 2016
    Publication date: September 13, 2018
    Inventors: Fabrice Devaux, Jean-François Roy
  • Publication number: 20180039586
    Abstract: A memory circuit having: a memory array including one or more memory banks (418); a first processor (420); and a processor control interface for receiving data processing commands directed to the first processor from a central processor (P1, P2), the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Application
    Filed: February 12, 2016
    Publication date: February 8, 2018
    Applicant: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 9335131
    Abstract: An emitter emits a wavelength included in the visible and/or infrared spectrum to illuminate a scene. An observation system is configured to deliver an image representative of the illuminated scene to an observer. The emitter is configured to deliver a light emission by at least one flash with a luminous power greater than a threshold generating dazzling. The observation system presents a first operating condition and a second operating condition of the observed scene to the observer, the second operating condition transmitting less luminous power than the first operating condition. A synchronization circuit is configured to synchronize the emitter and the observation system so that the observer is not dazzled during the emission phase of the emitter.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 10, 2016
    Assignee: BRISON S.A.
    Inventor: Fabrice Devaux
  • Publication number: 20160001163
    Abstract: The device for performing secured binding of a boot on a first ski includes a binding of the boot on the first ski and a control circuit. The binding is configured to facilitate disengagement between the boot and the first ski on receipt of a disengagement signal. A control circuit is configured to: determine an angular deviation between a first direction of the first ski and a second direction of a second ski, determine the forward progression of the first and second skis along the longitudinal axis of each of the skis, calculate at least one parameter from the angular deviation and from the forward progressions of the first and second skis, compare the parameter with a threshold parameter, and transmit the disengagement signal according to the comparison.
    Type: Application
    Filed: December 10, 2013
    Publication date: January 7, 2016
    Inventor: Fabrice DEVAUX
  • Publication number: 20150233682
    Abstract: An emitter emits a wavelength included in the visible and/or infrared spectrum to illuminate a scene. An observation system is configured to deliver an image representative of the illuminated scene to an observer. The emitter is configured to deliver a light emission by at least one flash with a luminous power greater than a threshold generating dazzling. The observation system presents a first operating condition and a second operating condition of the observed scene to the observer, the second operating condition transmitting less luminous power than the first operating condition. A synchronization circuit is configured to synchronize the emitter and the observation system so that the observer is not dazzled during the emission phase of the emitter.
    Type: Application
    Filed: September 6, 2013
    Publication date: August 20, 2015
    Inventor: Fabrice DEVAUX
  • Patent number: 8490085
    Abstract: A method for running, on a processor in non-privileged mode, different computer programs P while, in a nominal mode, using privileged instructions including running a hypervisor program in privileged mode of the processor, the hypervisor program providing the computer programs P with services substantially equivalent to those available for running in privileged mode, source codes of the computer programs P being modified beforehand for replacing the privileged instructions with calls for services supplied by the hypervisor program, and the hypervisor program creates at least two privileged submodes organized into a hierarchy within the non-privileged mode and the processor includes only two operating modes.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: July 16, 2013
    Assignee: VMware, Inc.
    Inventor: Fabrice Devaux
  • Patent number: 7966473
    Abstract: The invention concerns a method for read-addressing a site among a plurality of storage units using a coded address derived from an instruction. The method comprises the following steps: a) predicting (104) the storage unit corresponding to the site to be addressed; b) decoding (108) the address of the site to be addressed and determining (109) the storage unit to be addressed; c) managing (105) a potential read and rewrite conflict assuming that the predicted storage unit is the storage unit to be addressed; d) controlling (111) the addressing of the predicted storage unit at the end of the managing step (105); e) at the end of step b), determining (110) whether the storage unit to be addressed corresponds to the predicted storage unit; and f) if the storage unit to be addressed does not correspond to the predicted storage unit, managing (115) a possible read and rewrite conflict in the storage unit to be addressed and addressing the site of the storage unit to be addressed.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: June 21, 2011
    Assignees: STMicroelectronics S.A., Infineon Technologies AG
    Inventors: Jean-Paul Henriques, Fabrice Devaux
  • Publication number: 20070300219
    Abstract: A method for running, on a processor in non-privileged mode, different computer programs P while, in a nominal mode, using privileged instructions including running a hypervisor program in privileged mode of the processor, the hypervisor program providing the computer programs P with services substantially equivalent to those available for running in privileged mode, source codes of the computer programs P being modified beforehand for replacing the privileged instructions with calls for services supplied by the hypervisor program, and the hypervisor program creates at least two privileged submodes organized into a hierarchy within the non-privileged mode and the processor includes only two operating modes.
    Type: Application
    Filed: September 2, 2005
    Publication date: December 27, 2007
    Inventor: Fabrice Devaux
  • Patent number: 7209666
    Abstract: An all-optical clock recovery system for recovering the clock from a received optical signal with a short response time and without patterning effects includes a first optical clock recovery device adapted to supply a first optical clock signal in response to the received optical signal and a second optical clock recovery device adapted to supply a second optical clock signal in response to the first optical clock signal. Applications include regenerating optical packets in asynchronous optical packet-switched telecommunication networks.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: April 24, 2007
    Assignee: Alcatel
    Inventors: Dominique Chiaroni, Bruno Lavigne, Fabrice Devaux, Bernd Sartorius, Carsten Bornholdt, Stephan Bauer
  • Patent number: 7187869
    Abstract: The invention is also related to devices for a synchronization of data in an optical WDM transmission system, consisting of the following parts: A wavelength demultiplexer (1) for demultiplexing the incoming data stream in the synchronizer, delay lines (2) for the individual wavelength channels, a multiplexer (10), a modulator (3) modulated by a high frequency clock signal (5) and at least one photodetector (4) tapped to output line (B) where the photodetector (4) is connected to an electronic control circuit (6) which is connected to the findividual delay lines (2) for an automatic delay control.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: March 6, 2007
    Assignee: Alcatel
    Inventors: Fabrice Devaux, Patrick Brindel, Jean-Claude Jacquinot
  • Patent number: 6870977
    Abstract: A monolithic integrated optical component includes a control transistor connected to an electro-optical component including an active waveguide and at least one input waveguide and one output waveguide. The transistor is a heterojunction bipolar transistor including at least one sub-collector layer that is common to a confinement layer of the electro-optical component. The active waveguide of the electro-optical component includes a widened structure under a contact area of the heterojunction bipolar transistor and having substantially the same surface area as the transistor.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: March 22, 2005
    Assignee: Avanex Corporation
    Inventors: Fabrice Devaux, Sylvain Blayac, Philippe Andre