Abstract: The invention relates to a semiconductor device (1) comprising a stack of chips (C1; C) arranged in successive levels along a stacking direction, each chip extending in a main plane perpendicular to the stacking direction. The stack (E) comprises a plurality of chips (C1) of a first type comprising a first portion (P1) and a second portion (P2) each extending in the main plane, the first portion (P1) being liable to release more heat than the second portion (P2) when the chip is operating. Each chip of the first type (C1) is arranged in mechanical contact with a chip in an adjacent level of the stack (E) by way of a stacking surface that extends only over its second portion (P2), such that its first portion (P1) forms a projecting part able to be exposed to a cooling fluid.

Abstract: The invention relates to a method for protecting a memory device (1) from the effect of row hammering. The memory device (1) comprises a DRAM unit (U) formed by a plurality of memory point matrices (MAT1-MATN) subdivided into a plurality of memory blocks (B1-BM). The memory device (1) comprises activation counters (CTR1-CTRM) respectively associated with the memory blocks (B1-BM). The method comprises the execution, with each activation of a row of a given block (Bi), of a step of incrementing the activation counter (CTRi) associated with the given block (Bi); and the initiation of the preventive refresh of all the rows of the given block (Bi) when the activation counter (CTRi) of this given block (Bi) exceeds a threshold value (Si).

Abstract: A memory device comprises a DRAM unit formed by a plurality of memory point matrices subdivided into a plurality of memory blocks, and activation counters respectively associated with the memory blocks. The protection method comprises, with each activation of a row of a given block, incrementing the activation counter associated with a given block, and initiating a preventive refresh of all rows of the given block when the activation counter of this given block exceeds a threshold value. The method also comprises at least one of: including, in the preventive refresh, at least some of the rows of at least one block directly adjacent to the given block; incrementing, during activation of the row(s) of the given block, the activation counter of at least one directly adjacent block; and initiating the preventive refresh of all the rows of the adjacent block when the activation counter exceeds a threshold value.

Abstract: The invention relates to a memory device comprising:—DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102);—a control circuit configured to access the memory circuits, the control circuit comprising:—a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect;—a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

Abstract: The invention relates to a memory device comprising: —DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102); —a control circuit configured to access the memory circuits, the control circuit comprising: —a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect; —a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

Abstract: The invention relates to a memory device that comprises: —a memory bank provided with n memory rows, each row i being liable to effect a row hammer having a range p; —a block for preventing the hammer effect which comprises counting means implementing m hammer counters, each counter k being associated with one or more of the rows i, and is configured to increment a count k by an increment value kN, the increment value kN being a decreasing function of the duration TPN and also a function of the duration TAN, the increment value kN quantifying the effect of the hammer from the one or more rows i on rows j within hammering range; —a row refresh block configured to refresh one or more rows as soon as a count k reaches a threshold value M.

Abstract: The invention relates to a memory device comprising:—DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102); —a control circuit configured to access the memory circuits, the control circuit comprising:—a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect; —a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

Abstract: The invention relates to a method for protecting a memory device (1) from the effect of row hammering. The memory device (1) comprises a DRAM unit (U) formed by a plurality of memory point matrices (MAT1-MATN) subdivided into a plurality of memory blocks (B1-BM). The memory device (1) comprises activation counters (CTR1-CTRM) respectively associated with the memory blocks (B1-BM). The method comprises the execution, with each activation of a row of a given block (Bi), of a step of incrementing the activation counter (CTRi) associated with the given block (Bi); and the initiation of the preventive refresh of all the rows of the given block (Bi) when the activation counter (CTRi) of this given block (Bi) exceeds a threshold value (Si).

Abstract: The invention relates to a memory device comprising:—DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102); —a control circuit configured to access the memory circuits, the control circuit comprising:—a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect; —a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).

Abstract: The invention relates to a semiconductor device (1) comprising a stack of chips (C1; C) arranged in successive levels along a stacking direction, each chip extending in a main plane perpendicular to the stacking direction. The stack (E) comprises a plurality of chips (C1) of a first type comprising a first portion (P1) and a second portion (P2) each extending in the main plane, the first portion (P1) being liable to release more heat than the second portion (P2) when the chip is operating. Each chip of the first type (C1) is arranged in mechanical contact with a chip in an adjacent level of the stack (E) by way of a stacking surface that extends only over its second portion (P2), such that its first portion (P1) forms a projecting part able to be exposed to a cooling fluid.

Abstract: A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.

Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.

Abstract: A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.

Abstract: A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.

Abstract: A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Abstract: A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.

Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.