Abstract: A packet parser has a set of marker elements each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected.

Abstract: Embodied is a host network controller for a network processor. The host network controller is adapted to implement a finite state machine for an operation adhering to a standardized communication protocol, wherein the finite state machine has fewer possible states than those defined for the operation in accordance with the standardized communication protocol.

Abstract: Provided is a method for operating a host network controller for a network processor where the host network controller has at least one register. A restricted set of state data may be stored in at least one register. The restricted set of state data may be indicative of fewer possible states than those defined in accordance with a standardized communication protocol. The host network controller may implement a finite state machine based on the restricted set of state data stored in the at least one register such that the finite state machine may have fewer possible states than those defined in accordance with the standardized communication protocol.

Abstract: A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.

Abstract: A network interface controller for providing a connection for a device to a network. The network interface controller may include a sideband port controller. The sideband port controller may provide a sideband connection between the network and a sideband endpoint circuit that is operative to communicate information with the network via the sideband. The sideband port controller may include a transmit data route having an input for receiving packets from the sideband endpoint circuit and an output for passing packets received from the sideband endpoint to the network. A packet parser is connected to the transmit data route. The packet parser is operative to read data from packets received from the sideband endpoint and is further operative to analyze the data.

Abstract: Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.

Abstract: Aspects of the present disclosure are directed towards a network interface controller that could provide a connection for a device to a network. The network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyses a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.

Abstract: A network interface controller (NC) that can provide a connection for a device to a network. The NC can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can communicate information with the network via the sideband. The sideband port controller can include a receive data route that has an input for receiving packets of data from the network and an output for passing the packets of data received from the network to the sideband endpoint circuit. The receive data route may include a buffer to receive the packets of data from the network and to pass the packets of data received from the network to the sideband endpoint.

Abstract: A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.

Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

Abstract: Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.

Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.

Abstract: A data path for streaming data includes a plurality of sequential data registers, each of the plurality of sequential data registers comprising a plurality of data fields, wherein the streaming data moves sequentially through the sequential data registers; and a multiplexing unit, the multiplexing unit configured such that the multiplexing unit has access to each of the plurality of data fields of the plurality of sequential data registers, and wherein the multiplexing unit is configured to extract data from the streaming data as the streaming data moves through the sequential data registers in response to a data request.

Abstract: An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

Abstract: An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus? replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.

Abstract: An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus' replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.

Abstract: An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.

Abstract: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode.