Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.

Abstract: An apparatus and method are described, the apparatus comprising: a cache comprising a plurality of entries, each associated with a partition identifier; storage circuitry to store counters, each indicative of a number of entries in the cache associated with respective partition identifiers; and cache control circuitry responsive to a request identifying a given partition identifier to control allocation of an entry dependent on the counter associated with the given partition identifier. The cache control circuitry increments the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being allocated, and decrements the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being evicted or replaced.

Abstract: An apparatus and method are described, the apparatus comprising: a cache comprising a plurality of entries, each associated with a partition identifier; storage circuitry to store counters, each indicative of a number of entries in the cache associated with respective partition identifiers; and cache control circuitry responsive to a request identifying a given partition identifier to control allocation of an entry dependent on the counter associated with the given partition identifier. The cache control circuitry increments the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being allocated, and decrements the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being evicted or replaced.

Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.

Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data.

Abstract: Techniques are provided for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. Data is received at a PCS transmit structure from a MAC sublayer, and one or more alignment markers are inserted in the data. FEC encoding is performed, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data. The FEC encoded data is transmitted from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle, and the FEC encoded data is transmitted on one or more physical medium attachment (PMA) lanes to a PCS receive structure. FEC decoding is performed, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data.

Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data.

Abstract: Techniques are provided for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. Data is received at a PCS transmit structure from a MAC sublayer, and one or more alignment markers are inserted in the data. FEC encoding is performed, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data. The FEC encoded data is transmitted from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle, and the FEC encoded data is transmitted on one or more physical medium attachment (PMA) lanes to a PCS receive structure. FEC decoding is performed, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data.

Abstract: Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure.

Abstract: Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure.

Abstract: A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio. Data is transmitted from the first clock domain to the second clock domain without buffering the data.

Abstract: A method for reducing latency in a networking application includes receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, where the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further includes performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, where the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, where the first clock frequency and the second clock frequency have a fixed ratio. The data is transmitted from the first clock domain to the second clock domain without buffering the data. The method also includes performing one or more functions in the PCS on the data in the second clock domain.

Abstract: Proposed is an action machine for assembling response packets in a network processor. The action machine comprises: a first register array adapted to store data for entry into fixed-length fields of differing response packets, a fixed-length field having the same length in the differing response packets; and a second register array adapted to store data for entry into variable-length fields of differing response packets, a variable-length field having different values or lengths in the differing response packets. The action machine is adapted to assemble a response packet by combining data stored in the first register array with data stored in the second register array.

Abstract: Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit.

Abstract: Queue storage queues event entries from a hardware event detector that are to be communicated to a software event handler. An event register stores a most recently received event entry. A comparator compares a newly received event entry with the content of the event register and if a match occurs, then these event entries are merged by setting a merged entry bit and discarding the newly received event entry. When a non-matching event entry is received, then the unqueued event within the event register is stored into the queue storage. If the queue storage is empty, then the event register and the comparator are bypassed. When the queue storage becomes empty, then any currently unqueued event within the event register is stored into the queue storage. The event entries may be translation error event entries in a system which translates between virtual addresses and physical addresses.

Abstract: A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio.

Abstract: A method for reducing latency in a networking application includes receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, where the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further includes performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, where the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, where the first clock frequency and the second clock frequency have a fixed ratio. The data is transmitted from the first clock domain to the second clock domain without buffering the data. The method also includes performing one or more functions in the PCS on the data in the second clock domain.

Abstract: Queue storage queues event entries from a hardware event detector that are to be communicated to a software event handler. An event register stores a most recently received event entry. A comparator compares a newly received event entry with the content of the event register and if a match occurs, then these event entries are merged by setting a merged entry bit and discarding the newly received event entry. When a non-matching event entry is received, then the unqueued event within the event register is stored into the queue storage. If the queue storage is empty, then the event register and the comparator are bypassed. When the queue storage becomes empty, then any currently unqueued event within the event register is stored into the queue storage. The event entries may be translation error event entries in a system which translates between virtual addresses and physical addresses.

Abstract: Method and apparatus for reducing latency in a networking application comprises receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further comprises performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio. The method also comprises performing one or more functions in the PCS on the data in the second clock domain.

Abstract: Method and apparatus for reducing latency in a networking application comprises receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further comprises performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio. The method also comprises performing one or more functions in the PCS on the data in the second clock domain.