Patents by Inventor Fabrice Lallement
Fabrice Lallement has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9716029Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.Type: GrantFiled: June 20, 2012Date of Patent: July 25, 2017Assignee: SOITECInventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
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Patent number: 8999090Abstract: The invention relates to a method for bonding two substrates, in particular, two semiconductor substrates that, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.Type: GrantFiled: January 24, 2013Date of Patent: April 7, 2015Assignee: SOITECInventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard
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Patent number: 8946053Abstract: A method for reducing irregularities at a surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.Type: GrantFiled: June 20, 2011Date of Patent: February 3, 2015Assignee: SoitecInventors: Daniel Delprat, Carine Duret, Nadia Ben-Mohamed, Fabrice Lallement
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Publication number: 20140225182Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: SoitecInventors: Mohamad A. Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
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Publication number: 20140183601Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.Type: ApplicationFiled: June 20, 2012Publication date: July 3, 2014Applicant: SOITECInventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
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Patent number: 8735946Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: GrantFiled: September 16, 2013Date of Patent: May 27, 2014Assignee: SoitecInventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
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Publication number: 20140015023Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: SoitecInventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen
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Patent number: 8535996Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: GrantFiled: March 13, 2008Date of Patent: September 17, 2013Assignee: SOITECInventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
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Publication number: 20130071997Abstract: A method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.Type: ApplicationFiled: June 20, 2011Publication date: March 21, 2013Applicant: SOITECInventors: Daniel Delprat, Carine Duret, Nadia Ben-Mohamed, Fabrice Lallement
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Patent number: 8343850Abstract: A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.Type: GrantFiled: February 12, 2008Date of Patent: January 1, 2013Assignee: SoitecInventors: Eric Guiot, Fabrice Lallement
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Publication number: 20110183493Abstract: The present invention relates to a process for manufacturing a structure comprising a germanium layer (3) on a support substrate (1), characterised in that it comprises the following steps: (a) formation of an intermediate structure (10) comprising said support substrate (1), a silicon oxide layer (20) and said germanium layer (3), the silicon oxide layer (20) being in direct contact with the germanium layer (3), (b) application to said intermediate structure (10) of a heat treatment, in a neutral or reducing atmosphere, at a defined temperature and for a defined time, to diffuse at least part of the oxygen from the silicon oxide layer (20) through the germanium layer (3).Type: ApplicationFiled: June 12, 2009Publication date: July 28, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Nicolas Daval, Oleg Kononchuk, Eric Guiot, Cecile Aulnette, Fabrice Lallement, Christophe Figuet, Didier Landru
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Publication number: 20110012200Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.Type: ApplicationFiled: March 13, 2008Publication date: January 20, 2011Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Mohamad Shaheen, Carlos Mazure
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Publication number: 20110000612Abstract: The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates The invention also relates to a corresponding bonding equipmentType: ApplicationFiled: January 23, 2009Publication date: January 6, 2011Inventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard
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Publication number: 20100096733Abstract: A process for fabricating a substrate that includes a buried oxide layer for the production of electronic components or the like. The process includes depositing an oxide layer or a nitride layer on either of a donor or receiver substrate, and bringing the donor and receiver substrates into contact; conducting at least a first heat treatment of the oxide or nitride layer before bonding the substrates, and conducting a second heat treatment of the fabricated substrate of the receiver substrate, the oxide layer and all or part of the donor substrate at a temperature equal to or higher than the temperature applied in the first heat treatment. Substrates that have an oxide or nitride layer deposited thereon wherein the oxide or nitride layer is degassed and has a refractive index smaller than the refractive index of an oxide or nitride layer of the same composition formed by thermal growth.Type: ApplicationFiled: February 12, 2008Publication date: April 22, 2010Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Eric Guiot, Fabrice Lallement
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Patent number: 7416950Abstract: A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.Type: GrantFiled: February 9, 2006Date of Patent: August 26, 2008Assignee: STMicroelectronics S.A.Inventors: Damien Lenoble, Fabrice Lallement
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Publication number: 20060177976Abstract: A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.Type: ApplicationFiled: February 9, 2006Publication date: August 10, 2006Applicant: STMicroelectronics S.A.Inventors: Damien Lenoble, Fabrice Lallement