Abstract: A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field.

Abstract: A method for scrambling a calculation involving at least one operation, of which at least one intermediary result takes into account at least one secret quantity, including modifying the intermediary result with a random quantity, carrying on the calculation with the modified result, and restoring an expected result at the end of the calculation.

Abstract: The operation Y0=(X*J0) mod 2Bt is implemented directly within a coprocessor to eliminate the need for, a register of Bt=m*k bits within the coprocessor. This eliminated register enables the storage of a data element during the computation of Y0. The operation S=A*B mod 2m*k is implemented with a circuit including at least three registers and a multiplication circuit. One of the registers simultaneously stores S and an intermediate result. To improve the method, a second multiplication circuit and registers of variable sizes are used.

Abstract: The computation time of modular operations on large-format data is improved by using a computation circuit integrated as a modular arithmetic coprocessor. The computation circuit carries out an S=A*B+C type operation, with S and C encoded on 2*Bt bits, and A and B encoded on Bt bits. To carry out this operation, a storage flip-flop circuit enables the storage of a possible overflow carry value at the end of an elementary computation, and reinserts this carry value during the following computation.