Patents by Inventor Fabrice Semond
Fabrice Semond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522346Abstract: The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: formation (100) of a buffer layer (20) on a substrate (10), said buffer layer comprising an upper surface layer based on group III nitrides, and deposition (200) of a crystalline layer (30) on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides. The invention also relates to a support obtained by the method, to a semiconductor structure based on the support, and to the method for the production thereof.Type: GrantFiled: January 21, 2016Date of Patent: December 31, 2019Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)Inventors: Fabrice Semond, Eric Frayssinet, Jean Massies
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Patent number: 10361077Abstract: The invention relates to a method for producing a semiconductor structure, characterized in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, ??) and (0, ??) between the central line (0, 0) and the integer order line (0, ?1), and two fractional order diffraction lines (0, ?) and (0, ?) between the central line (0, 0) and the integer order line (0, 1).Type: GrantFiled: January 21, 2016Date of Patent: July 23, 2019Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)Inventors: Fabrice Semond, Eric Frayssinet, Jean Massies
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Publication number: 20180019120Abstract: The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: formation (100) of a buffer layer (20) on a substrate (10), said buffer layer comprising an upper surface layer based on group III nitrides, and deposition (200) of a crystalline layer (30) on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides. The invention also relates to a support obtained by the method, to a semiconductor structure based on the support, and to the method for the production thereof.Type: ApplicationFiled: January 21, 2016Publication date: January 18, 2018Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)Inventors: Fabrice SEMOND, Eric FRAYSSINET, Jean MASSIES
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Publication number: 20180012753Abstract: The invention relates to a method for producing a semiconductor structure, characterised in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, ??) and (0, ??) between the central line (0, 0) and the integer order line (0, ?1), and two fractional order diffraction lines (0, ?) and (0, ?) between the central line (0, 0) and the integer order line (0, 1).Type: ApplicationFiled: January 21, 2016Publication date: January 11, 2018Applicant: Centre National de la Recherche Scientifique (CNRS)Inventors: Fabrice SEMOND, Eric FRAYSSINET, Jean MASSIES
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Publication number: 20110084310Abstract: A method of manufacture of a optical, photonic or optoelectronic component, including a so-called photonic slab or membrane that is traversed, in at least one internal region and according to a predetermined pattern, by a plurality of through openings having a micrometric or sub-micrometric transverse dimension, the method having the following steps: structuring of the surface of a substrate by an etching that produces holes in the substrate according to the pattern; depositing at least one layer of the photonic material forming the slab or membrane, by anisotropic epitaxial growth on the structured surface of the substrate around the opening of the holes.Type: ApplicationFiled: January 19, 2009Publication date: April 14, 2011Applicant: Universite Paris-SudInventors: Sylvain David, Philippe Boucaud, Fabrice Semond
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Patent number: 7785991Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.Type: GrantFiled: November 16, 2007Date of Patent: August 31, 2010Assignee: STMicroelectronics SAInventors: Sylvain Joblot, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz
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Patent number: 7776154Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: GrantFiled: August 1, 2007Date of Patent: August 17, 2010Assignee: Picogiga International SASInventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
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Patent number: 7767307Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: GrantFiled: August 1, 2007Date of Patent: August 3, 2010Assignee: Centre National de la Recherche ScientifiqueInventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
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Publication number: 20090294776Abstract: Silicon layer highly sensitive to oxygen and method for obtaining said layer. This layer (2), formed on a substrate (4) for example of SiC, has a 3'2 structure. To obtain it, it is possible to substantially uniformly deposit silicon on a surface of the substrate. The invention can be applied for example to microelectronics.Type: ApplicationFiled: July 4, 2006Publication date: December 3, 2009Applicants: Commissarita A L'Energie Atomique, Universite Paris Sud (Paris XI)Inventors: Patrick Soukiassian, Fabrice Semond
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Publication number: 20080188065Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: August 7, 2008Applicant: Centre National De La Recherche Scientifique (CNRS)Inventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Publication number: 20080185611Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: August 7, 2008Applicant: Centre National De La Recherche Scientifique (CNRS)Inventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Publication number: 20080149936Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.Type: ApplicationFiled: November 16, 2007Publication date: June 26, 2008Applicant: STMICROELECTRONICS SAInventors: SYLVAIN JOBLOT, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz
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Publication number: 20080050894Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: February 28, 2008Applicant: PICOGIGA INTERNATIONAL SASInventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Publication number: 20080048207Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: August 1, 2007Publication date: February 28, 2008Applicant: PICOGIGA INTERNATIONAL SASInventors: Fabrice SEMOND, Jean MASSIES, Nicolas GRANDJEAN
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Patent number: 7273664Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: GrantFiled: June 8, 2001Date of Patent: September 25, 2007Assignee: Picogiga International SASInventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
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Publication number: 20040132242Abstract: According to the invention, parallel atomic lines (4) are formed on the surface of a substrate (2) in silicon carbide, and a material is deposited on this surface, able to be adsorbed selective fashion between the atomic lines and not on these atomic lines, the depositing of this material thereby generating strips (6,8) of this material between the atomic lines.Type: ApplicationFiled: October 20, 2003Publication date: July 8, 2004Inventors: Marie D'Angelo, Victor Aristov, Vincent Derycke, Fabrice Semond, Patrick Soukiassian
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Publication number: 20030136333Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.Type: ApplicationFiled: December 9, 2002Publication date: July 24, 2003Inventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
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Patent number: 6445009Abstract: A device includes a silicon substrate provided with a coating including at least one stacking constituted by a plane of GaN or GaInN quantum dots emitting visible light at room temperature in a respective layer of AIN or GaN. The method of making the device is also disclosed. The device can be incorporated in electroluminescent devices and exchange devices, emitting white light in particular.Type: GrantFiled: August 8, 2000Date of Patent: September 3, 2002Assignee: Centre National de la Recherche ScientifiqueInventors: Nicolas Pierre Grandjean, Jean Massies, Benjamin Gérard Pierre Damilano, Fabrice Semond, Mathieu Leroux
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Patent number: 6274234Abstract: Atomic wires of great length and great stability are formed on the surface of a SiC substrate as straight chains of dimers of an element chosen from amongst SiC and C. In order to produce same, layers of the element are formed on the surface and the assembly is constructed by means of annealings of the surface provided with the layers. The resulting wires have application to nanoelectronics.Type: GrantFiled: June 14, 1999Date of Patent: August 14, 2001Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche ScientifiqueInventors: Gérald Dujardin, Andrew Mayne, Fabrice Semond, Patrick Soukiassian