Abstract: The present invention discloses CRC checking 'N-bit at a time' of data frames of lengths not necessarily in a multiple of the N-bit. While receiving the data frame, the data frame length is extracted from the protocol header and a misalignment is computed versus the 'N-bit at a time' value. Simultaneously, CRC is computed on each received N-bit of the data frame and an FCS register is updated. At each cycle, a checking is performed to know whether the data frame length has been extracted from the protocol header. While the data frame length is not yet known and more bits are left to process, the data frame is continued to be received and computed 'N-bit at a time'. When the data frame length is known and no more bits are to be processed, the current value of the FCS register is compared to a pre-stored vector corresponding to the misalignment. If a match occurs, checking of the data frame passes and the data frame is accepted.

Abstract: A method and system for testing a plurality of filter rules in a computer system is disclosed. The plurality of filter rules uses at least one range of values in at least one dimension. Each range includes a minimum and a maximum value. The filter rules are used with a key. The method and system include reducing an amount of testing required based on the minimum and maximum value of each range to ensure that the key can match a portion of the filter rules and testing the key against the portion of the filter rules. In one aspect, the method and system include determining at least one subset of filter rules and testing the key against each subset to determine whether the key matches a filter rule of a subset. The subset of filter rules is non-intersecting in at least a second dimension and is based on the minimum value and the maximum value of each range in the second dimension.

Abstract: An improved arbiter is described for arbitrating requests by a plurality of first data processing units for access to a plurality of second data processing units interconnected by a switching system of a type in which at any time each first unit can only access one second unit and each second unit can only be accessed by one first unit. The arbiter comprises a scheduler mechanism for repeatedly selecting access requests with a defined minimum probability of selecting a request for each first unit-second unit combination. Rearrangement storage means records requests selected by the scheduler mechanism. A rearranger is provided for repeatedly selecting a set of requests recorded in the rearrangement storage means, so that only one request per first unit and per second unit is selected, using a priority mechanism which increases the probability of selection with the length of time a request is stored in the rearrangement storage means.

Abstract: A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full.

Abstract: Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.

Abstract: An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

Abstract: The invention discloses a method and an apparatus for use in high speed networks such as Asynchronous Transfer Mode (ATM) networks providing support for processing multipriority data flows at media speed, the major constraint being to share the storage and the ALU between all the tasks. The invention consists first in grouping the tasks in processes and the processes in set of processes all organized in decreasing order of their priority ; `on the fly`interruption of a lower priority process/set of processes by a higher priority process/set of processes is possible as well as reuse of the shared resources during task void states inactive in a process or between processes.In the preferred embodiment of the invention, the support of the reserved bandwidth and non reserved bandwidth ATM services data flows requires two different groups of processes, the highest priority being for the group of processes serving the reserved bandwidth service.

Abstract: The method and apparatus of the present invention solve the problem of scheduling the transmission of cells in packet switched networks having network connections requiring a minimum bandwidth at connection establishment. The method and the apparatus further support any mixed traffic flow including connections requiring a minimum bandwidth, a fixed reserved bandwidth or no bandwidth at connection establishment. Scheduling is controlled by a dual scheduling mechanism having a first scheduler, triggered by absolute time, for scheduling the minimum service connections up to a rate corresponding to their reserved minimum bandwidth, a second scheduler and a queue of minimum service connection identifiers for communication between the two scheduling schemes.

Abstract: The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports.

Abstract: A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of a message sent over a connection and segmented into a finite number of packets in a fixed size packets network. The process is implemented in the adapter cards of the ATM network access nodes (2, 4) located at the boundary of the ATM network. These nodes, when supporting AAL5 type ATM connections, reassemble messages which have been segmented at the entry of the network and to calculate the FCS of the message cell payloads for data integrity checking. The process of the invention starts at each reception of a cell with the calculation of a partial FCS (10) performed in parallel to the connection control block fetching phase (40); these 2 parallel operations allow FCS checking during the cell processing time of connections established over medium and high speed lines.

Abstract: The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.

Abstract: A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.

Abstract: An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.

Abstract: A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.

Abstract: A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46).

Abstract: A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.

Abstract: A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.

Abstract: The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

Abstract: A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.

Abstract: An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.