Abstract: The present disclosure relates to a NFC communication system, to a method of establishing communication between a wireless communication device and a passive NFC device and to a passive NFC device. The passive NFC device includes an NFC controller, an NFC transceiver coupled with the NFC controller, and at least one persistent flag coupled with the NFC controller, the persistent flag being switchable between an activated state and a deactivated state. The NFC controller is configured to perform a logical operation being divisible into a sequence of at least a first subtask and a second subtask and the NFC controller is configured to ascertain the status of the persistent flag. The NFC controller is further configured to selectively perform at least one of the first subtask and the second subtask on the basis of the status of the persistent flag.

Abstract: The present disclosure relates to a NFC communication system, to a method of establishing communication between a wireless communication device and a passive NFC device and to a passive NFC device. The passive NFC device includes an NFC controller, an NFC transceiver coupled with the NFC controller, and at least one persistent flag coupled with the NFC controller, the persistent flag being switchable between an activated state and a deactivated state. The NFC controller is configured to perform a logical operation being divisible into a sequence of at least a first subtask and a second subtask and the NFC controller is configured to ascertain the status of the persistent flag. The NFC controller is further configured to selectively perform at least one of the first subtask and the second subtask on the basis of the status of the persistent flag.

Abstract: A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

Abstract: A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.

Abstract: This method uses a tester (T) capable of being connected to an integrated circuit (CI) to be tested. A random number (RNG-C) is generated and ciphered using a key (k) by a cipher algorithm to obtain a password (Gk(RNG)-C). The random number (RNG-C) is sent to the tester (T) in which the received random number (RNG-C) is ciphered using the same key (k) by a same cipher algorithm to generate therein a second password (Gk(RNG)-T). This latter is sent to the integrated circuit (CI) to be compared to the first password (Gk(RNG)-C). The test of the confidential parts (1) of the circuit is only authorised if the two passwords exhibit the required match.

Abstract: The invention concerns an integrated circuit, particularly for a smart card, including a central unit (1), a non-volatile memory (9) capable of containing the machine code and data, and a memory control unit (8). The integrated circuit is characterized in that the memory control unit includes programmable allocation means (10) for allocating first (9a) and second (9b) spaces of the non volatile memory defined for containing, respectively, the machine code and the data.

Abstract: The integrated circuit is provided with integrated calibrating circuit in order to calibrate at least one electronic module supplying at its output a reference voltage or a time base signal or a reference frequency signal. Said calibrating means are defined by a microcontroller which receives via an input pad of the integrated circuit an external reference signal which is compared to an internal reference signal of the reference module in order to be able to calibrate in an autonomous manner the integrated reference electronic module as a function of the external reference signal. The final calibrating parameters are permanently stored with an associated signature in a memory so that each time that voltage is subsequently applied to the circuit the final calibrating parameters are automatically applied to the corresponding reference module.

Abstract: This method uses a tester (T) capable of being connected to an integrated circuit (CI) to be tested.

Abstract: The integrated circuit (1) is provided with integrated calibrating means in order to be able to calibrate at least one electronic module (9) supplying at its output a reference voltage or a time base signal or a reference frequency signal. Said calibrating means are defined by a microcontroller which receives via an input pad (2) of the integrated circuit (1) an external reference signal (3) which is compared to an internal reference signal of the reference module in order to be able to calibrate in an autonomous manner the integrated reference electronic module (9) as a function of the external reference signal (3). The final calibrating parameters are permanently stored with an associated signature in a memory (10) so that each time that voltage is subsequently applied to the circuit said final calibrating parameters are automatically applied to the corresponding reference module (9).