Abstract: The present invention relates to a device for treatment of an ocular pathology, the device comprising at least one eye ring (1) wherein the proximal end of said eye ring (1) is suitable to be applied onto the globe and means (2) to generate ultrasound beam fixed on the distal end of the eye ring (1), said means to generate ultrasound beam presenting a concave segment shape conformed along a single curvature corresponding to a single direction wherein the concavity is designed to be tuned towards the eyeglobe.

Abstract: A phacoemulsificator for the removal of lens tissue, said phacoemulsificator comprising: a power source (31) configured to provide pulsed electrical power, and a pump (32) configured to provide vacuum, characterized in that the phacoemulsificator comprises at least one eye ring (1) connectable to the pump wherein the proximal end of said eye ring (1) is suitable to be applied onto an ocular globe and means (2) to generate ultrasound beam connectable to the power source wherein said means are fixed on the distal end of the eye ring (1).

Abstract: A device for treatment of an ocular pathology characterized in that it comprises at least one eye ring (1) wherein the proximal end of said eye ring (1) is suitable to he applied onto the globe and means (2,17) to generate ultrasound beam fixed on the distal end of the eye ring (1), said means to generate ultrasound beam presenting a concave segment shape conformed along a single curvature corresponding to a single direction wherein the concavity is designed to be tuned towards the eyeglobe.

Abstract: The present invention relates to a method of treating an ocular pathology by generating high intensity focused ultrasound onto at least one eye's area, said method comprises at least the following steps of: —positioning onto the eye a device capable of directing high intensity focused ultrasound onto at least one annular segment, —and generating high intensity focused ultrasound energy onto said segment to treat at least one annular segment in the eye. Another embodiment of the invention concerns a device for treatment of an ocular pathology comprising at least one eye ring (1) wherein the proximal end of said eye ring (1) is suitable to be applied onto the globe and circular means (2,17) to generate ultrasound beam fixed on the distal end of the eye ring (1) capable of treating the whole circumference of the eye in one step.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: A programmable delay line is introduced that produces a delayed signal that is glitch free and without metastability conditions. The programmable delay line includes a synchronizer circuit and a programmable delay circuit. The synchronizer circuit is configured to receive an input signal and one or more control signals. The synchronizer circuit synchronizes the one or more control signals to the input signal, producing one or more synchronized control signals. The programmable delay circuit is configured to utilizing the synchronized control signals to add an amount of delay to the input signal, producing a delayed version of the input signal that is glitch free and without metastability conditions. The control signals control the amount of delay added to the input signal based on, for example, process, voltage and temperature (PVT) variations.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal, an IO device output node, and a common ground node. The IO device also includes a first driver having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together, a plurality of third n-channel or p-channel FETs each having a drain coupled to the IO device input node, and a plurality of first capacitors coupled between the common ground node and respective sources of the plurality of third n-channel or p-channel FETs. The drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node, while the gate of the first n-channel FET is coupled to the IO device input node.

Abstract: An input circuit for an integrated circuit for interfacing an external signal line external to the integrated circuit includes first circuit means having an input that may be coupled to the signal line to provide a regenerated signal at their output, and second circuit means having an input coupled to receive the regenerated signal and driving the external signal line. The external signal line can thus be maintained at a predetermined logic level, even in the absence of any driving on the external signal line. Third circuit means are provided that are capable of providing to the second circuit means a supply voltage equal to the greater of a supply voltage of the integrated circuit to which the input circuit belongs, and the voltage existing on the external signal line.