Abstract: A system for generating motion vectors in a motion estimator is configured for co-operating with an engine for calculating estimation error for generating motion vectors, according to estimation errors and/or motion vectors previously generated. The system comprises a program memory that contains program data for a motion-estimation algorithm, and a motion-vector memory that contains data identifying said motion vectors previously calculated.

Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.

Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.

Abstract: A method of estimating the motion field of a digital picture sequence includes subdividing a current picture to examine in an integer number of macroblocks, for each macroblock of the current picture determining a search window centered on a macroblock of a preceding picture placed in the same position of the considered macroblock of the current picture, carrying out a motion estimation between the considered macroblock of the current picture and the macroblock most similar to it included in the window. At least a dimension of the search window is established as a function of the corresponding dimension of the search window used for the preceding picture, the estimated motion field of the preceding picture and certain threshold values.

Abstract: A process for realizing an estimate of global motion based on a sequence of subsequent video images, such as those received via an optical mouse (M) for the purposes of detecting its movement.

Abstract: A processing architecture enables execution of one first set of instructions and one second set of instructions compiled for being executed by two different CPUs, the first set of instructions not being executable by the second CPU, and the second set of instructions not being executable by the first CPU. The architecture comprises a single CPU configured for executing both the instructions of the first set and the instructions of the second set. The single CPU in question being selectively switchable between a first operating mode, in which the single CPU executes the first set instructions, and a second operating mode, in which the single CPU executes the second set of instructions. The single processor is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction.

Abstract: Interface circuitry is disclosed for interfacing between an operational circuit, a microprocessor, for example, and data storage circuitry, for example direct Rambus memory. The interface circuitry comprises buffer circuitry coupled between the operational circuitry and the data storage circuitry which is arranged to store data access requests received from the operational circuitry and to store data retrieved from the data storage circuitry. The buffer circuitry comprises an output for supplying the data access request signals to the data storage circuitry and to supply the stored data from the data storage circuitry to the operational circuitry. In use, the number of stored data access request signals decreases as the amount of stored data from the data storage circuitry increases. Similarly, the number of stored data access request signals increases as the amount of stored data from the data storage circuitry decreases.

Abstract: A method for recognizing a progressive or an interlaced content of video pictures during their processing in a coder includes performing a number of operations on at least one of the luminance or chrominance components of the video signal. A macroblock belonging to a frame of a preceding picture is defined, and a first pair of coefficients on the selected luminance or chrominance component of the video signal is calculated. A first counter is incremented at each positive verification when one of the coefficients is greater than the other coefficient by a determined amount. A second counter is incremented at each macroblock being tested. A second pair of coefficients is calculated for each row of each Top semi-frame. A third counter is incremented at each positive verification when one of the coefficients is greater than the other coefficient by a determined amount. A fourth counter is incremented at each row tested.

Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.

Abstract: A coprocessor circuit for processing image data in digital form, having a motion vector controller block for generating, starting from said image data, motion vector values. Such vector values include predictor data and macroblock data relating to a current macroblock of said image data to be estimated, the prediction data and macroblock data being adapted to be stored at respective memory addresses. An address generator block is provided for extracting said respective addresses from said motion vector values. A predictor fetch block for retrieving said predictor data based on respective addresses extracted by said address generator block, a current macroblock fetch and distengine block for retrieving said macroblock data based on respective addresses extracted by said address generator block and for processing said macroblock data according to a given function, all provided, as well as a decision block for collecting said retrieved data as partial results and selecting the best result therefrom.

Abstract: A motion estimation process in video signals organized in successive frames divided into macroblocks that is carried out by the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centered on the central position to which the best motion vector points and the distance of the points of the grid from the center is defined as a function of the matching error typically consisting of an SAD function, defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.

Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver.

Abstract: A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.

Abstract: A memory interface is disclosed for accessing a plurality in memory regions. The interface includes a register which stores a number of memory request signals received from a processor or the like. The memory interface includes circuitry for detecting which memory region each memory request refers to and also which page within that memory region is required to be accessed. Using the information contained in the register, the memory interface is able to determine which page within a memory region will be required to be accessed after the currently open page is closed. The memory interface can detect this information a number of memory requests in advance. Thus the memory interface is able to provide the necessary control instructions to initiate the opening of the subsequently required page within a memory region so that when the memory request requiring access to this page is serviced, there is no delay in opening the page.