Abstract: An Extensible Markup Language (XML) based storage handling controller for a storage medium is provided. The XML based storage handling controller includes storage handling firmware that is in communication with a storage medium. The storage handling firmware is capable of receiving and generating XML based data, which is utilized for configuring the storage handling firmware. In addition, a basic input out input output system (BIOS) is included that is in communication with the storage handling firmware. The BIOS includes a browser capable of presenting XML based data. The browser can provide a graphical user interface (GUI) that can be used to provide configuration commands to the storage handling firmware.

Abstract: A method for configuring a Redundant Array of Inexpensive Disks (RAID) host adapter card is provided. The RAID host adapter card includes a flash storage chip and a RAID input/output processor (IOP). The RAID host adapter card is coupled to a peripheral connection interface (PCI) bus of a computer system and is interconnected to at least one storage container. The computer system has a system memory. The method includes booting the computer system and passing control to the RAID IOP. The RAID IOP reads the flash storage chip to execute a fraction of code previously written to the flash storage chip. The RAID IOP further communicates to the hard drive to locate a main portion of code previously written to at least one hidden sector. The RAID IOP also loads the main portion of the code to the system memory of the computer system to enable interoperability of the host adapter card with the computer system.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: A method for configuring channels of a dual channel SCSI chip is provided which includes setting at least one bit in a first configuration space within a first channel control in the dual channel SCSI chip where the first configuration space returns a device identification information when accessed by an operating system. The method also includes setting at least one bit in a second configuration space within a second channel control in the dual channel SCSI chip where the second configuration space returns data indicating that the second configuration space does not contain any device identification information when accessed by the operating system. The first channel control is detected and managed by the operating system, and the second channel control is not detected by the operating system and is managed by a device processor.

Abstract: Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary method includes receiving a request from a system BIOS to locate an amount of conventional memory where the amount of conventional memory accommodates at least a decompressed version of data located in an option ROM BIOS. Then the amount of conventional memory requested by the system BIOS is determined. If the amount of conventional memory requested by the system BIOS is not available, the method continues and system BIOS data located within the conventional memory is read where the system BIOS data occupies at least the amount of conventional memory requested by the system BIOS. After the system BIOS data is read, the system BIOS data is written from the conventional memory to an extended memory, and the system BIOS data located in the conventional memory that has been written into the extended memory is deleted.

Abstract: A method for utilizing a multi-channel SCSI chip capable of controlling different types of devices is disclosed. A first channel control is set and a second channel control is set in the SCSI chip. A first peripheral device type is managed using the first channel control and a second peripheral device type is managed using the second channel control.

Abstract: Methods of conserving memory resources available to a computer system during execution of a system BIOS are provided. The method includes (a) executing the system BIOS; (b) loading the header, runtime code, and memory allocator code associated with the option ROM BIOS chip into the option ROM memory space; (c) passing control to the memory allocator code; (d) executing the memory allocator code to allocate conventional memory of the system RAM; (e) copying the decompressor code from the option ROM BIOS chip to the allocated conventional memory; (f) passing control to the decompressor code; (g) executing the decompressor code to decompress the compressed initialization code directly from the option ROM BIOS chip and thus loading the decompressed initialization code into the conventional memory; and (h) executing the decompressed initialization code to initialize the adapter card or controller.

Abstract: A boot sequence adapted for use with a computer system during execution of system BIOS to ensure compatibility between an option ROM BIOS chip and a chip of interest with which the option ROM BIOS chip is intended to communicate during operation of the computer system is provided. The boot sequence may broadly include the operations of initially locating the chip of interest and then sequentially scanning each of option ROM BIOS chip's images until a determination is made that a match exists between the unique PCI device ID associated with the chip of interest and the image PCI device ID associated with a scanned one of the BIOS images. The boot sequence then ensures that the first BIOS image incorporates the unique PCI device ID associated with the chip of interest, after which the first BIOS image is loaded into system RAM for execution of the BIOS routine.

Abstract: A boot sequence adapted for use with a computer system during execution of system BIOS. The computer system includes a random access memory (RAM), a selected number of controllers. Each of the controllers reside in a respective expansion slot (e.g., PCI slot), have at least one drive associated therewith, and have an option read only memory (Option ROM) that includes a BIOS initialization code and a runtime code.