Patents by Inventor Fadi Busaba

Fadi Busaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9626189
    Abstract: Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Busaba, David Hutton, John G. Rell, Jr., Chung-Lung K. Shum
  • Patent number: 9582315
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. Optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Publication number: 20160162329
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. Optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Application
    Filed: January 28, 2016
    Publication date: June 9, 2016
    Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9292337
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Michael K Gschwind, Valentina Salapura, Chung-Lung Shum
  • Patent number: 9292357
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Publication number: 20160004559
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Application
    Filed: September 15, 2015
    Publication date: January 7, 2016
    Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9135005
    Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, James R. Mitchell
  • Patent number: 9104399
    Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
  • Publication number: 20150169358
    Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Fadi Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung Shum
  • Patent number: 8938605
    Abstract: A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Bruce Giamei, David Hutton, Eric Schwarz
  • Patent number: 8645669
    Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi
  • Publication number: 20130339670
    Abstract: Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Busaba, David Hutton, John G. Rell, JR., Chung-Lung K. Shum
  • Patent number: 8495341
    Abstract: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, Wen Li
  • Patent number: 8464030
    Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: June 11, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Brian Curran, Lee Eisen, Bruce Giamei, David Hutton
  • Patent number: 8082467
    Abstract: A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gregory W. Alexander, Fadi Busaba, David A. Schroter, Eric Schwarz, Brian W. Thompto, Wesley J. Ward, III
  • Publication number: 20110276764
    Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 10, 2011
    Applicant: International Business Machines Corporation
    Inventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi
  • Publication number: 20110252220
    Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 13, 2011
    Applicant: International Business Machines Corporation
    Inventors: Fadi BUSABA, Brian CURRAN, Lee EISEN, Bruce GIAMEI, David HUTTON
  • Publication number: 20110219213
    Abstract: A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.
    Type: Application
    Filed: March 5, 2010
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Fadi BUSABA, Bruce GIAMEI, David HUTTON, Eric SCHWARZ
  • Publication number: 20110202747
    Abstract: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, Wen Li
  • Publication number: 20110185158
    Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: International Business Machines Corporation
    Inventors: KHARY J. ALEXANDER, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, James R. Mitchell