Patents by Inventor Fadi Busaba
Fadi Busaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9626189Abstract: Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.Type: GrantFiled: June 15, 2012Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi Busaba, David Hutton, John G. Rell, Jr., Chung-Lung K. Shum
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Patent number: 9582315Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. Optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: GrantFiled: January 28, 2016Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Publication number: 20160162329Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. Optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: ApplicationFiled: January 28, 2016Publication date: June 9, 2016Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 9292337Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: GrantFiled: December 12, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Fadi Busaba, Michael K Gschwind, Valentina Salapura, Chung-Lung Shum
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Patent number: 9292357Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: GrantFiled: September 15, 2015Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Publication number: 20160004559Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Inventors: Fadi Busaba, Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
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Patent number: 9135005Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.Type: GrantFiled: January 28, 2010Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, James R. Mitchell
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Patent number: 9104399Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.Type: GrantFiled: December 23, 2009Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
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Publication number: 20150169358Abstract: A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. wherein optimized machine instructions are generated based on an intermediate representation of a program, wherein either two atomic tasks are merged into a single coalesced transaction or are executed as separate transactions.Type: ApplicationFiled: December 12, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Fadi Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung Shum
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Patent number: 8938605Abstract: A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.Type: GrantFiled: March 5, 2010Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Fadi Busaba, Bruce Giamei, David Hutton, Eric Schwarz
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Patent number: 8645669Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The first set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.Type: GrantFiled: May 5, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi
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Publication number: 20130339670Abstract: Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi Busaba, David Hutton, John G. Rell, JR., Chung-Lung K. Shum
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Patent number: 8495341Abstract: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.Type: GrantFiled: February 17, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, Wen Li
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Patent number: 8464030Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.Type: GrantFiled: April 9, 2010Date of Patent: June 11, 2013Assignee: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Lee Eisen, Bruce Giamei, David Hutton
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Patent number: 8082467Abstract: A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.Type: GrantFiled: December 23, 2009Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Gregory W. Alexander, Fadi Busaba, David A. Schroter, Eric Schwarz, Brian W. Thompto, Wesley J. Ward, III
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Publication number: 20110276764Abstract: A method, information processing system, and computer program product manage computer executable instructions. At least one machine instruction for execution is received. The at least one machine instruction is analyzed. The machine instruction is identified as a predefined instruction for storing a variable length first operand in a memory location. Responsive to this identification and based on fields of the machine instruction, a relative location of a variable length second operand of the instruction with location of the first operand is determined. Responsive to the relative location having the predefined relationship, a first cracking operation is performed. The first cracking operation cracks the instruction into a first set of micro-ops (Uops) to be executed in parallel. The second set of Uops is for storing a first plurality of first blocks in the first operand. Each of said first block to be stored are identical. The first set Uops are executed.Type: ApplicationFiled: May 5, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Khary J. Alexander, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi
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Publication number: 20110252220Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: International Business Machines CorporationInventors: Fadi BUSABA, Brian CURRAN, Lee EISEN, Bruce GIAMEI, David HUTTON
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Publication number: 20110219213Abstract: A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.Type: ApplicationFiled: March 5, 2010Publication date: September 8, 2011Applicant: International Business Machines CorporationInventors: Fadi BUSABA, Bruce GIAMEI, David HUTTON, Eric SCHWARZ
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Publication number: 20110202747Abstract: A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Applicant: International Business Machines CorporationInventors: Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, Wen Li
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Publication number: 20110185158Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: International Business Machines CorporationInventors: KHARY J. ALEXANDER, Fadi Busaba, Brian Curran, Bruce Giamei, Christian Jacobi, James R. Mitchell