Abstract: Various embodiments are generally directed to techniques for accurate evaluation of a financial portfolio. Techniques described herein may include an apparatus comprising: a processing circuit; and an approximate computing engine, executed on the processing circuit, operative to process data items corresponding to prices of funds, compute a Net Asset Value (NAV) based on the data items, determine a precision associated with the Net Asset Value (NAV), and based upon a precision metric, determine whether to use the Net Asset Value (NAV) in a business decision. Other embodiments are described.

Abstract: Systems, methods, apparatuses, and computer-readable media for guaranteed quality of service (QoS) in cloud computing environments. A workload related to an immutable log describing a transaction may be received. A determination is made based on the immutable log that a first compute node stores at least one data element to process the transaction. Utilization levels of computing resources of the first compute node may be determined. Utilization levels of links connecting the first compute node to the fabric may be determined. A determination may be made, based on the utilization levels, that processing the workload on the first compute node satisfies one or more QoS parameters specified in a service level agreement (SLA). The workload may be scheduled for processing on the first compute node based on the determination that processing the workload on the first compute node satisfies the one or more QoS parameters specified in the SLA.

Abstract: Systems, methods, apparatuses, and computer-readable media for guaranteed quality of service (QoS) in cloud computing environments. A workload related to an immutable log describing a transaction may be received. A determination is made based on the immutable log that a first compute node stores at least one data element to process the transaction. Utilization levels of computing resources of the first compute node may be determined. Utilization levels of links connecting the first compute node to the fabric may be determined. A determination may be made, based on the utilization levels, that processing the workload on the first compute node satisfies one or more QoS parameters specified in a service level agreement (SLA). The workload may be scheduled for processing on the first compute node based on the determination that processing the workload on the first compute node satisfies the one or more QoS parameters specified in the SLA.

Abstract: Various embodiments are generally directed to techniques for accurate evaluation of a financial portfolio. Techniques described herein may include an apparatus comprising: a processing circuit; and an approximate computing engine, executed on the processing circuit, operative to process data items corresponding to prices of funds, compute a Net Asset Value (NAV) based on the data items, determine a precision associated with the Net Asset Value (NAV), and based upon a precision metric, determine whether to use the Net Asset Value (NAV) in a business decision. Other embodiments are described.

Abstract: Systems, methods, apparatuses, and computer-readable media for guaranteed quality of service (QoS) in cloud computing environments. A workload related to an immutable log describing a transaction may be received. A determination is made based on the immutable log that a first compute node stores at least one data element to process the transaction. Utilization levels of computing resources of the first compute node may be determined. Utilization levels of links connecting the first compute node to the fabric may be determined. A determination may be made, based on the utilization levels, that processing the workload on the first compute node satisfies one or more QoS parameters specified in a service level agreement (SLA). The workload may be scheduled for processing on the first compute node based on the determination that processing the workload on the first compute node satisfies the one or more QoS parameters specified in the SLA.

Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

Abstract: A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.

Abstract: A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

Abstract: A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

Abstract: A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal.

Abstract: A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.