Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

Abstract: A method for synthesis of MgH2/Ni nanocomposites includes balancing magnesium (Mg) powder in a ball milling container with helium (He) gas atmosphere; adding a plurality of nickel (Ni) milling balls to the container; introducing hydrogen (H2) gas to the container to form a MgH2 powder; milling the MgH2 powder using the Ni-balls as milling media to provide MgH2/Ni nanocomposites. The milling can be high-energy ball milling, e.g., under 50 bar of hydrogen gas atmosphere. The high-energy ball milling can be reactive ball milling (RBM). The method can be used to attach Ni to MgH2 powders to enhance the kinetics of hydrogenation/dehydrogenation of MgH2.

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

Abstract: A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.

Abstract: A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract: A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.

Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.

Abstract: A Continuous Ambulatory Hemofilter includes an outer casing, multifunction pump, hemofilter, reverse osmosis filter, power source, drainage bag, blood lines and fluid lines, characterized in that the hemofiltrate from the hemofilter is moved to a reverse osmosis filter. The ultrafiltrate fluid from the reverse osmosis filter flows to the out-flow tube of the hemofilter vein line through a dedicated fluid line. The exit of the reverse osmosis filter is connected to a drainage bag. The multifunction pump moves blood from a permanent jugular catheter to the hemofilter, and fluids between the hemofilter, reverse osmosis filter, vein line and drainage bag. An electrode is placed at the in-flow tube of the hemofilter to measure incoming blood osmolality. The electrode is connected to a microprocessor that is further connected to a computer-controlled valve at the out-flow line of the reverse osmosis filter. The microprocessor is connected with a memory card.

Abstract: A Continuous Ambulatory Haemofiltration consisting of an outer casing, multifunction pump, haemofilter, reversed osmosis filter, power source, drainage bag, blood lines and fluid lines, characterized in that the haemofiltrate from the haemolfilter is moved to a reversed osmosis filter. The ultrafiltrate fluid from the reversed osmosis filter flows to the out-flow tube of the haemofilter veineus line through a specific fluid line. The exit of the reversed osmosis filter is connected to a drainage bag. The multifunction pump moves blood from the jagular perm catherter to the haemofilter, and fluids between the haemofilter, reversed osmosis filter, veineus line and drainage bag. An electrode is placed at the in-flow tube of the haemofilter to measure incoming blood osmolality. The electrode is connected to a microprocessor that is further connected to a computer-controlled valve at the out-flow line of the reversed osmosis filter. The microprocessor is connected with a memory card.