Abstract: A vertical chemical vapor deposition (CVD) reactor and a method for synthesizing metal oxide impregnated carbon nanotubes. The CVD reactor includes a preheating zone portion and a reaction zone portion, and preferably an additional cooling zone portion and a product collector. The method includes (a) subjecting a liquid reactant solution comprising an organic solvent, a metallocene, and a metal alkoxide to atomization in the presence of a gas flow comprising a carrier gas and a support gas to form an atomized mixture, and (b) heating the atomized mixture to a temperature of 200° C.?1400° C., wherein the heating forms a metal oxide and at least one carbon source compound, wherein the metallocene catalyzes the formation of carbon nanotubes from the at least one carbon source compound and the metal oxide is incorporated into or on a surface of the carbon nanotubes to form the metal oxide impregnated carbon nanotubes.

Abstract: A vertical chemical vapor deposition (CVD) reactor and a method for synthesizing metal oxide impregnated carbon nanotubes. The CVD reactor includes a preheating zone portion and a reaction zone portion, and preferably an additional cooling zone portion and a product collector. The method includes (a) subjecting a liquid reactant solution comprising an organic solvent, a metallocene, and a metal alkoxide to atomization in the presence of a gas flow comprising a carrier gas and a support gas to form an atomized mixture, and (b) heating the atomized mixture to a temperature of 200° C.-1400° C., wherein the heating forms a metal oxide and at least one carbon source compound, wherein the metallocene catalyzes the formation of carbon nanotubes from the at least one carbon source compound and the metal oxide is incorporated into or on a surface of the carbon nanotubes to form the metal oxide impregnated carbon nanotubes.

Abstract: A method for preparing multi-wall carbon nanotubes comprising atomizing a precursor solution comprising an aromatic hydrocarbon and a carrier gas. The mixture is then injected through an ultrasonic atomization system to form atomized precursor droplets. Then by injecting the atomized precursor droplets from the top of a vertical chemical vapor deposition reactor, the droplets can then react with a reaction gas in the reactor vessel to form a film that adsorbs to a growth surface in the reactor vessel. Layer by layer multi-wall carbon nanotubes are formed. This method is repeated to form layers of the multi-wall carbon nanotubes. The nanotubes formed have an outer diameter of 10 nm-51 nm and a length to diameter aspect ratio of 7200-13200.

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting example. A tapped-delay line(s) is included in the data flow paths between memory and execution units in the VPE. The tapped-delay line (s) is configured to receive and provide an input vector data sample set to execution units for performing correlation/covariance vector processing operations.

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting example. A tapped-delay line(s) is included in the data flow paths between memory and execution units in the VPE. The tapped-delay line (s) is configured to receive and provide an input vector data sample set to execution units for performing correlation/covariance vector processing operations.

Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

Abstract: Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads the IP module to process input data in response to handshake signal; and a data processor generating output data and a modified handshake signal after processing a handshake signal and input data under the control of the controller. The present invention makes it possible to design an IP module that is easily reusable and optimized in architecture, lightening effort and time for designing and verifying an SOC by means of the proposed IP module.