Patents by Inventor Fahmida FERDOUSI

Fahmida FERDOUSI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-planar semiconductor device having hybrid geometry-based active region
    Patent number: 11139400
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Google LLC
    Inventors: Seiyon Kim, Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn
  • NON-PLANAR SEMICONDUCTOR DEVICE HAVING HYBRID GEOMETRY-BASED ACTIVE REGION
    Publication number: 20200185526
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 11, 2020
    Inventors: Seiyon KIM, Rafael RIOS, Fahmida FERDOUSI, Kelin J. KUHN
  • Non-planar semiconductor device having hybrid geometry-based active region
    Patent number: 10593804
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn
  • Non-planar semiconductor device having hybrid geometry-based active region
    Patent number: 10586868
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn
  • NON-PLANAR SEMICONDUCTOR DEVICE HAVING HYBRID GEOMETRY-BASED ACTIVE REGION
    Publication number: 20180358467
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 13, 2018
    Inventors: Seiyon KIM, Rafael RIOS, Fahmida FERDOUSI, Kelin J. KUHN
  • Non-Planar Semiconductor Device Having Hybrid Geometry-Based Active Region
    Publication number: 20160276484
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Application
    Filed: December 19, 2013
    Publication date: September 22, 2016
    Inventors: Seiyon KIM, Rafael RIOS, Fahmida FERDOUSI, Kelin J. KUHN