Abstract: An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: In a non-volatile memory, a programming cycle consists of the following phases: high voltage charging up, programming pulse, and discharge. The actual programming process only takes place in the programming pulse phase. Several break points are defined relative to elapsed time and introduced in the programming pulse phase. Upon receiving a suspend request, the programming operation will advance to the next break point, then discharge the high programming voltage and go to a suspend state. A separate counter is used to monitor the break points so that elapsed non-programming time can be deducted from the total programming pulse time when the programming operation is resumed. By doing so, the device can handle frequent suspend and resume requests. Since the total time duration in the programming pulse phase is equal for the programming operation with and without suspend and resume requests, the programming proceeds efficiently to completion.

Abstract: An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: In a non-volatile memory, a programming cycle consists of the following phases: high voltage charging up, programming pulse, and discharge. The actual programming process only takes place in the programming pulse phase. Several break points are defined relative to elapsed time and introduced in the programming pulse phase. Upon receiving a suspend request, the programming operation will advance to the next break point, then discharge the high programming voltage and go to a suspend state. A separate counter is used to monitor the break points so that elapsed non-programming time can be deducted from the total programming pulse time when the programming operation is resumed. By doing so, the device can handle frequent suspend and resume requests. Since the total time duration in the programming pulse phase is equal for the programming operation with and without suspend and resume requests, the programming proceeds efficiently to completion.

Abstract: A nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory intended to be used as a relatively permanent program memory and an E.sup.2 PROM intended to be used as a more frequently updated data memory. A single set of address lines and a single set of data lines are used for both read and write operations for both memory arrays. Address decoding means for accessing an addressed location of a selected memory array includes separate column decoders and data latches for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory. Data I/O buffer circuitry and sense amplifiers are also shared by both arrays.