Patents by Inventor Faisal A. Syed
Faisal A. Syed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11829320Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: GrantFiled: October 20, 2022Date of Patent: November 28, 2023Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Publication number: 20230061478Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: ApplicationFiled: October 20, 2022Publication date: March 2, 2023Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Patent number: 11550750Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: GrantFiled: July 17, 2020Date of Patent: January 10, 2023Assignee: Coherent Logix, IncorporatedInventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Publication number: 20210034566Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: ApplicationFiled: July 17, 2020Publication date: February 4, 2021Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Patent number: 10747709Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: GrantFiled: November 2, 2018Date of Patent: August 18, 2020Assignee: COHERENT LOGIX, INCORPORATEDInventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Publication number: 20190138492Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.Type: ApplicationFiled: November 2, 2018Publication date: May 9, 2019Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
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Patent number: 8410833Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.Type: GrantFiled: March 30, 2011Date of Patent: April 2, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Michael A. Nix, Golam R. Chowdhury, Curtis M. Brody, Faisal A. Syed
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Publication number: 20120218012Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.Type: ApplicationFiled: March 30, 2011Publication date: August 30, 2012Inventors: Michael A. Nix, Golam R. Chowdhury, Curtis M. Brody, Faisal A. Syed
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Patent number: 7929361Abstract: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.Type: GrantFiled: March 31, 2008Date of Patent: April 19, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Patent number: 7872937Abstract: A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.Type: GrantFiled: March 31, 2008Date of Patent: January 18, 2011Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Patent number: 7869287Abstract: A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.Type: GrantFiled: March 31, 2008Date of Patent: January 11, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Patent number: 7685406Abstract: A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then modified based upon the number of bytes associated with the stack dependent operation. A current location in the stack is determined based on the stack pointer and the stack pointer delta.Type: GrantFiled: March 22, 2007Date of Patent: March 23, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Christopher Svec, Faisal Syed, Michael E. Tuuk, Benjamin T. Sander, Gregory W. Smaus
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Publication number: 20090244996Abstract: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Publication number: 20090245010Abstract: A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Publication number: 20090244995Abstract: A receive circuit (320) includes a DLL core (510), a latch (326), and a DLL control circuit (520). The DLL core (510) has a first input for receiving a DLL clock signal, a second input for receiving a delay line select signal, and an output for providing a delayed data strobe signal. The latch (326) has a signal input for receiving an external data signal, a control input coupled to the output of the DLL core (510), and an output for providing an internal data signal. The DLL control circuit (520) provides the DLL clock signal to the first input of the DLL core (510) responsive to a memory data strobe signal while the receive circuit is in a first mode, and provides the DLL clock signal to the first input of the DLL core (510) responsive to a processor clock signal while the receive circuit (320) is in a second mode.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Shawn Searles, Faisal A. Syed, Nicholas T. Humphries
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Publication number: 20080235491Abstract: A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then modified based upon the number of bytes associated with the stack dependent operation. A current location in the stack is determined based on the stack pointer and the stack pointer delta.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicant: Advanced Micro Devices, Inc.Inventors: Christopher Svec, Faisal Syed, Michael E. Tuuk, Benjamin T. Sander, Gregory W. Smaus