Abstract: A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional serial communications link features are implemented are able to perform the lane polarity reversal and lane order reversal functions. Integrated circuits in which the optional serial communications link features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: Integrated circuits compliant with a serial communications protocol with optional features are provided. The optional features include control plane features such as flow control, retry-on-error, clock tolerance compensation, and idle codes and include data path features such as streaming and packetized data modes, configurable data ports and user-defined data channel multiplexing. An integrated circuit compliant with the protocol can transmit streaming data with or without clock tolerance compensation codes. A priority data port can be used to implement retry-on-error functions while user-defined data channels carry user data. The data ports can be individually configured to perform different levels of cyclic redundancy checking. Logic design tools are used to create compliant circuits and systems.

Abstract: The lane skew alignment device of the present invention facilitates the use of the SFI-5 standard interface in an FPGA without the need to rely on feedback signals from a remote device. The delay between lanes is determined using a D-Flip Flop or other type of phase comparator. To minimize the components needed to physically implement the solution a cross-point switch is used to select one of the parallel lanes at a time to be compared to a reference lane, over which the same test signal is transmitted.

Abstract: Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ?X/N? groups of cells; a read-write control block receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for the group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of the group of cells are stored in the N memory modules; the MCP address being the same as the group address.

Abstract: A serial communications protocol with optional and adjustable data link layer and physical layer features is provided. A logic design tool for designing circuits compliant with the protocol is also provided. Using the logic design tool, desired optional protocol features may be included to enhance circuit functionality and undesired optional protocol features may be omitted to conserve circuit resources. The logic design tool may include design aids related to retry-on-error timeout calculations, FIFO sizing, transmitter and receiver circuit parameters, and other design parameters. A user of the logic design tool can view information provided by the logic design tool's design aids and can make design selections.

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into [X/N] groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;