Abstract: A communication circuit is disclosed. The communication circuit includes a calibration system, configured to receive clock signals respectively having first and second clock phases, and first and second duty cycles, where the calibration system is further configured to receive input data and to adjust the input data to generate adjusted data based partly on the input data and based partly on the first and second duty cycles. The communication circuit also includes a mixer, configured to receive the clock signals and to receive the adjusted data, where the mixer is configured to generate output data based on the clock signals and the adjusted data, and where a mismatch in the output data caused by the first and second duty cycles being different is reduced because of the adjustment made to the input data to generate the adjusted data.

Abstract: Techniques are described herein for phase modulation and interpolation that support high phase modulation resolution with high linearity. Embodiments receive a digital signal that uses a sequence of K-bit digital codes to encode a sequence of instantaneous phases for phase-modulating a local oscillator signal. A fractional divider divides a reference clock into N divided clock signals at equally spaced phase intervals and selects a pair of such signals based on first designated bits of the digital code. A fractional divider-calibrated delay line generates M delayed clock signals at equally spaced phase intervals between the selected pair of divided clock signals, and selects a pair of the delayed clock signals based on second designated bits of the digital code. A digital controlled edge interpolator generates a delayed local oscillator output signal by interpolating between the selected pair of delayed clock signals based on third designated bits of the digital code.

Abstract: A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

Abstract: A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Abstract: An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.

Abstract: A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Abstract: A receiver circuit includes a mixer receiving an RF signal encoding an information signal. The mixer receives a number of multiphase oscillator signals and generates multiphase baseband signals. The receiver circuit also includes a variable gain circuit receives the multiphase baseband signals, generates a first output signal having a first distortion, and a second output signal having a second distortion. The variable gain circuit is configured to generate a reduced distortion output signal based on the first and second output signals.

Abstract: A receiver circuit includes a mixer receiving an RF signal encoding an information signal. The mixer receives a number of multiphase oscillator signals and generates multiphase baseband signals. The receiver circuit also includes a variable gain circuit receives the multiphase baseband signals, generates a first output signal having a first distortion, and a second output signal having a second distortion. The variable gain circuit is configured to generate a reduced distortion output signal based on the first and second output signals.

Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

Abstract: A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.

Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Abstract: Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.

Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

Abstract: Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.

Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Abstract: A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.

Abstract: A method for controlling a load-current zero-crossing of a switching regulator having a high-side switch and a low-side switch includes detecting, by a spike detection circuit, a presence of a spike on an output voltage of the switching regulator, determining, by the spike detection circuit, in the event that a spike is present, whether the spike is a positive spike or a negative spike, and adjusting a turn-off timing of the low-side switch based on a determination result.

Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.