Abstract: A vector operation capability is integrated into the execution unit (E-Unit) portion of a computing systems central processing unit (CPU) designed to support scalar instruction processing. The fixed point and floating point instruction functional units in the E-Unit that are required to implement the vector instruction set are pipelined. A set of vector registers are added to the architected data registers contained in the E-Unit. The E-Unit control logic is modified to queue and schedule both vector and scalar instructions, The E-Unit's load and store unit bandwidth capability to support the transfer of the contiguous blocks of data normally associated with vector processing are enhanced. The integrated vector and scalar capability allows for improved processing of programs that include both vector and scalar type instructions.