Patents by Inventor Fakhruddin ALI BOHRA

Fakhruddin ALI BOHRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111711
    Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Lalit Gupta, Yew Keong Chong, Gus Yeung
  • Publication number: 20210110853
    Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.
    Type: Application
    Filed: October 12, 2019
    Publication date: April 15, 2021
    Inventors: Lalit Gupta, Nicolaas Klarinus Johannes van Windelhoff, Bo Zheng, El Mehdi Boujamaa, Fakhruddin Ali Bohra
  • Publication number: 20210110867
    Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 15, 2021
    Inventors: Lalit Gupta, Bo Zheng, Fakhruddin Ali Bohra, Nimish Sharma, Nicolaas Klarinus Johannes Van Winkelhoff, El Mehdi Boujamaa
  • Publication number: 20210110851
    Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 15, 2021
    Inventors: Lalit Gupta, Nicolaas Klarinus Johannes Van Winkelhoff, El Mehdi Boujamaa, Bo Zheng, Fakhruddin Ali Bohra, Cyrille Nicolas Dray, Ashish Bhardwaj, Durgesh Kumar Dubey
  • Publication number: 20210098032
    Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Lalit Gupta, Bo Zheng, El Mehdi Boujamaa, Fakhruddin Ali Bohra
  • Patent number: 10943670
    Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Gaurav Rattan Singla
  • Publication number: 20210065839
    Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Inventors: Lalit Gupta, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Gaurav Rattan Singla
  • Patent number: 10878892
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10873324
    Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 22, 2020
    Assignee: Arm Limited
    Inventors: Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Lalit Gupta, Yew Keong Chong, Gus Yeung
  • Publication number: 20200388309
    Abstract: Various implementations described herein are directed to a device having an array of bitcells with bitlines coupled to columns of the bitcells. The device may include one or more switch structures that are coupled between the bitlines and a supply voltage, and the switch structures may be configured to precharge the bitlines to the supply voltage when activated. In some instances, the supply voltage may refer to ground or a ground related voltage having a voltage near or equal to zero volts (0V).
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Lalit Gupta, Gaurav Rattan Singla, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10839861
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
  • Patent number: 10755774
    Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 25, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10748583
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 18, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10734065
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Navin Agarwal, Shri Sagar Dwivedi, Jitendra Dasani, Fakhruddin Ali Bohra, Lalit Gupta, Daksheshkumar Maganbhai Malaviya
  • Publication number: 20200219559
    Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Inventors: Vivek Nautiyal, Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10672459
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Arm Limited
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10622038
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla
  • Patent number: 10600477
    Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 24, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Publication number: 20200014373
    Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Lalit Gupta, Yew Keong Chong, Gus Yeung
  • Publication number: 20200005836
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla