Patents by Inventor Falgun G. Trivedi
Falgun G. Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875865Abstract: A method includes determining a programmed threshold voltage for a select gate of a memory string and assigning the select gate a programmed reliability rank based upon the programmed threshold voltage. The programmed reliability rank indicates that hot data, warm data, and/or or cold data are programmable to the memory string. The method further includes incrementing a quality characteristic count to a first check voltage value, determining a first checked threshold voltage for the select gate at the first check voltage value, and assigning the select gate a first reliability rank based upon the first checked threshold voltage. The first reliability rank indicates that the warm data or the cold data, or both, are programmable to the memory string.Type: GrantFiled: February 11, 2022Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventor: Falgun G. Trivedi
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Patent number: 11869607Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.Type: GrantFiled: June 13, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventor: Falgun G. Trivedi
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Publication number: 20230207029Abstract: A method includes determining a programmed threshold voltage for a select gate of a memory string and assigning the select gate a programmed reliability rank based upon the programmed threshold voltage. The programmed reliability rank indicates that hot data, warm data, and/or or cold data are programmable to the memory string. The method further includes incrementing a quality characteristic count to a first check voltage value, determining a first checked threshold voltage for the select gate at the first check voltage value, and assigning the select gate a first reliability rank based upon the first checked threshold voltage. The first reliability rank indicates that the warm data or the cold data, or both, are programmable to the memory string.Type: ApplicationFiled: February 11, 2022Publication date: June 29, 2023Inventor: Falgun G. Trivedi
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Patent number: 11670376Abstract: Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.Type: GrantFiled: June 7, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Falgun G. Trivedi, Motao Cao
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Publication number: 20220392540Abstract: Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Falgun G. Trivedi, Motao Cao
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Patent number: 11513889Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: August 26, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
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Publication number: 20220328110Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.Type: ApplicationFiled: June 13, 2022Publication date: October 13, 2022Inventor: Falgun G. Trivedi
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Patent number: 11361837Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.Type: GrantFiled: December 9, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventor: Falgun G. Trivedi
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Publication number: 20220180947Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventor: Falgun G. Trivedi
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Publication number: 20210390014Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: August 26, 2021Publication date: December 16, 2021Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
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Patent number: 11106530Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 20, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
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Publication number: 20210191807Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang