Patents by Inventor Falk Graetsch

Falk Graetsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150137270
    Abstract: A transistor device includes a gate electrode structure. The gate electrode structure includes a high-k gate insulation layer, a metal-containing first electrode material positioned above the high-k gate insulation layer, and a second electrode material positioned above the metal-containing first electrode material. The high-k gate insulation layer has a length that is less than a length of the second electrode material.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 8951901
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 8445344
    Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 21, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Richard Carter, Falk Graetsch, Martin Trentzsch, Sven Beyer, Berthold Reimer, Robert Binder, Boris Bayha
  • Patent number: 8283232
    Abstract: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: October 9, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Publication number: 20120086056
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Application
    Filed: July 22, 2011
    Publication date: April 12, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 7897450
    Abstract: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fabian Koehler, Katy Schabernack, Falk Graetsch
  • Publication number: 20100327373
    Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 30, 2010
    Inventors: Richard Carter, Falk Graetsch, Martin Trentzsch, Sven Beyer, Berthold Reimer, Robert Binder, Boris Bayha
  • Publication number: 20100304542
    Abstract: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Publication number: 20090246371
    Abstract: A thermally activated batch process is disclosed for forming thin material layers in semiconductor devices including the establishment of an overheating temperature profile prior to actually forming a material layer, for instance, by deposition, so that a gas depletion at the centre of the substrate during the deposition process be compensated for. Thus, enhanced thickness uniformity for thin material layers in the range of 1 to 50 nanometers may be obtained without additional process time or even at a reduced process time.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 1, 2009
    Inventors: Fabian Koehler, Falk Graetsch
  • Publication number: 20090242999
    Abstract: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.
    Type: Application
    Filed: January 16, 2009
    Publication date: October 1, 2009
    Inventors: Fabian Koehler, Katy Schabernack, Falk Graetsch
  • Publication number: 20050233532
    Abstract: The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.
    Type: Application
    Filed: January 19, 2005
    Publication date: October 20, 2005
    Inventors: Markus Lenski, Falk Graetsch, Carsten Reichel, Christoph Schwan, Helmut Bierstedt, Thorsten Kammler, Martin Mazur
  • Patent number: 6900111
    Abstract: A method for forming a reliable and ultra-thin oxide layer, such as a gate oxide layer of an MOS transistor, comprises an annealing step immediately performed prior to oxidizing a substrate. The annealing step is performed in an inert gas ambient to avoid oxidation of the semiconductor surface prior to achieving a required low oxidizing temperature. Preferably, the annealing step and the oxidizing step are carried out as an in situ process, thereby minimizing the thermal budget of the overall process.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 31, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Stephan Krügel, Falk Graetsch
  • Patent number: 6875676
    Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: April 5, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Gunter Grasshoff
  • Patent number: 6812159
    Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Publication number: 20040192057
    Abstract: The present invention provides a technique for forming extremely thin insulation layers requiring the incorporation of specified amounts of nitrogen, wherein the effect of nitrogen variations across the substrate surface may be reduced in that during and/or after the nitrogen incorporation an oxidation process is performed. The nitrogen variations lead to a nitrogen concentration dependent oxidation rate and, hence, a nitrogen concentration dependent thickness variation of the insulating layer. In particular, the threshold variations of transistors including the thin insulating layer as a gate insulation layer may effectively be reduced.
    Type: Application
    Filed: October 24, 2003
    Publication date: September 30, 2004
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Patent number: 6723663
    Abstract: For aggressively scaled field effect transistors, nitrogen is incorporated into a base oxide layer, wherein, at an initial phase of a plasma nitridation process, the nitrogen ion density is maintained at a value so that incorporation of nitrogen into the channel region is minimized. Subsequently, when the thickness of the base oxide layer has increased, due to residual oxygen in the plasma ambient, the nitrogen ion density is increased, thereby increasing the nitridation rate. Preferably, the nitrogen ion density is controlled by varying the pressure of the plasma ambient. Moreover, a system is disclosed that allows control of the nitridation rate in response to an oxide layer thickness.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Patent number: 6703278
    Abstract: A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: March 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Stephan Kruegel
  • Publication number: 20040043627
    Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
    Type: Application
    Filed: April 22, 2003
    Publication date: March 4, 2004
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Publication number: 20040016974
    Abstract: A highly localized diffusion barrier is incorporated into a polysilicon line to allow the doping of the polysilicon layer without sacrificing an underlying material layer. The diffusion barrier is formed by depositing a thin polysilicon layer and exposing the layer to a nitrogen-containing plasma ambient. Thereafter, the deposition is resumed to obtain the required final thickness. Moreover, a polysilicon line is disclosed, having a highly localized barrier layer.
    Type: Application
    Filed: February 6, 2003
    Publication date: January 29, 2004
    Inventors: Karsten Wieczorek, Falk Graetsch, Gunter Grasshoff
  • Publication number: 20030157772
    Abstract: A method of forming oxide layers of different thickness on a substrate is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.
    Type: Application
    Filed: July 30, 2002
    Publication date: August 21, 2003
    Inventors: Karsten Wieczorek, Falk Graetsch, Stefan Kruegel