Abstract: A method of operating a laboratory sample distribution system is presented. The system comprises container carriers, a gateway having a network interface, and transport modules. Each module comprises a transport surface and are adjacent in a row-direction and column-direction to form a transport surface. The module comprises a driver arranged below the transport surface to move container carriers on the transport surface and left, right, upper and lower network interfaces. The left and right network interfaces connect modules in rows and the upper and lower network interfaces connect modules in columns. The network interface of the gateway is connected to a network interface of a first module. The method comprises sending an explore command from the gateway to the first module, propagating an initialization command from the first module to the remaining modules, storing addresses within the modules, and using the addresses by the gateway to address the modules.

Abstract: A method of operating a laboratory sample distribution system is presented. The system comprises container carriers, a gateway having a network interface, and transport modules. Each module comprises a transport surface and are adjacent in a row-direction and column-direction to form a transport surface. The module comprises a driver arranged below the transport surface to move container carriers on the transport surface and left, right, upper and lower network interfaces. The left and right network interfaces connect modules in rows and the upper and lower network interfaces connect modules in columns. The network interface of the gateway is connected to a network interface of a first module. The method comprises sending an explore command from the gateway to the first module, propagating an initialization command from the first module to the remaining modules, storing addresses within the modules, and using the addresses by the gateway to address the modules.

Abstract: It is difficult to optimize the timing of the forward and reverse direction for high frequency bi-directional digital signals. Therefore, a digital system is provided that improves the adjustability of the timing by the emission of an additional clock pulse, together with the output clock pulse for the receiver and the feedback clock pulse for the PLL. The additional clock pulse is re-circulated using a delay line and is used to set the clock pulse of the reverse direction signals.

Abstract: The performance of digital signals depends to a great extent on the frequency. However, the higher the frequency, the shorter the remaining time, in which digital signals can be reliably received by a receiver from a driver via a printed conductor. The run time of the clock pulse and signals must be optimized in such a way that no timing losses occur at any location, even in the extreme environmental conditions. The invention improves the timing and minimizes external influences by coupling the output signals to an internal PLL clock pulse.

Abstract: A memory architecture and a copy machine is described in which a dirty tag memory is segmented to permit more rapid access to dirty data addresses for subsequent copying.