Abstract: A computer-implemented method for managing cache utilization of at least a first processor when sharing a cache with a further processor. The method includes: executing, during a first regulation interval, a first application on a first processor, wherein the first application causes at least one block to be mapped from an external memory to a shared cache according to a cache utilization policy associated with the first application; monitoring a utilization of the shared cache by the first processor during the first regulation interval; comparing the utilization of the shared cache by the first processor to a cache utilization condition associated with the first processor; and adjusting the cache utilization policy associated with the first application, when the utilization of the shared cache by the first processor exceeds the cache utilization condition associated with the first processor.

Abstract: A method for operating a processing unit, in which a multiplicity of processes are carried out, which together access a resource according to a predefined resource distribution. The method includes a determination of an instantaneous actual processing time of at least one of the multiplicity of processes during an execution of the at least one of the multiplicity of processes, within which the at least one of the multiplicity of processes is processed; a comparison of the actual processing time with a setpoint processing time assigned to the at least one of the multiplicity of processes and/or with a sum of the assigned setpoint processing time and a processing time extension assigned to the at least one of the multiplicity of processes; and an adaptation of the predefined resource distribution as a function of a result of this comparison.

Abstract: A method for operating a cache memory having a set having multiple memory blocks configured for storing data blocks. In a write process of a data block into a memory block of the set, the data block is written into the memory block, a relevance rank value of the data block and a first access time rank value are determined. Rank data associated with the memory block are determined using a write rank mapping from the relevance rank value and the first access time rank value, and the determined rank data are stored. If no memory block of the set is free, a memory block that is to be overwritten is selected from the memory blocks of the set based on the rank data, which are associated with the memory blocks, and the data block to be stored is written into the selected memory block by using the write process.

Abstract: A method for dynamically assigning memory bandwidth to multiple processor units, which are connected via a data connection to a shared memory unit. In an initialization phase, each of the multiple processor units are assigned an initial value of a usable memory bandwidth, and a permissible range for a mean usage of the memory bandwidth is determined. Subsequently, the assigned memory bandwidths are checked repeatedly and adjusted if needed, a present value of a mean usage of the memory bandwidth by the multiple processor units being determined, and, if this present value is outside the permissible range, the values of the usable memory bandwidth are adjusted for at least a part of the multiple processor units.

Abstract: A device and a computer-implemented method for a neural architecture search. A first set of values is provided for parameters that define at least one part of an architecture for an artificial neural network, wherein the part of the architecture encompasses a plurality of layers of the artificial neural network and/or a plurality of operations of the artificial neural network, wherein a first value of a function is determined for the first set of values for the parameters, said first value characterizing a property of a target system when the target system executes a task for the part of the artificial neural network that is defined by the first set of values for the parameters.

Abstract: A computer-implemented method for managing cache utilization of at least a first processor when sharing a cache with a further processor. The method includes: executing, during a first regulation interval, a first application on a first processor, wherein the first application causes at least one block to be mapped from an external memory to a shared cache according to a cache utilization policy associated with the first application; monitoring a utilization of the shared cache by the first processor during the first regulation interval; comparing the utilization of the shared cache by the first processor to a cache utilization condition associated with the first processor; and adjusting the cache utilization policy associated with the first application, when the utilization of the shared cache by the first processor exceeds the cache utilization condition associated with the first processor.

Abstract: A computer-implemented method for managing memory areas of a memory unit in a processing unit. The method includes determining, upon occurrence of a predefined event, a memory configuration profile according to which individual processes are in each case allowed to access individual memory areas of the memory unit, configuring the memory unit according to the determined memory configuration profile in such a way that the individual processes are in each case allowed to access individual memory areas of the memory unit, analyzing a performance of the processing unit while the particular processes are being executed in the processing unit and are accessing the individual memory areas according to the determined memory configuration profile, and providing a result of the analysis which describes the performance of the processing unit as a function of the determined memory configuration profile.

Abstract: A method for operating a cache memory having a set having multiple memory blocks configured for storing data blocks. In a write process of a data block into a memory block of the set, the data block is written into the memory block, a relevance rank value of the data block and a first access time rank value are determined. Rank data associated with the memory block are determined using a write rank mapping from the relevance rank value and the first access time rank value, and the determined rank data are stored. If no memory block of the set is free, a memory block that is to be overwritten is selected from the memory blocks of the set based on the rank data, which are associated with the memory blocks, and the data block to be stored is written into the selected memory block by using the write process.

Abstract: A method for operating a processing unit, in which a multiplicity of processes are carried out, which together access a resource according to a predefined resource distribution. The method includes a determination of an instantaneous actual processing time of at least one of the multiplicity of processes during an execution of the at least one of the multiplicity of processes, within which the at least one of the multiplicity of processes is processed; a comparison of the actual processing time with a setpoint processing time assigned to the at least one of the multiplicity of processes and/or with a sum of the assigned setpoint processing time and a processing time extension assigned to the at least one of the multiplicity of processes; and an adaptation of the predefined resource distribution as a function of a result of this comparison.

Abstract: A method for dynamically assigning memory bandwidth to multiple processor units, which are connected via a data connection to a shared memory unit. In an initialization phase, each of the multiple processor units are assigned an initial value of a usable memory bandwidth, and a permissible range for a mean usage of the memory bandwidth is determined. Subsequently, the assigned memory bandwidths are checked repeatedly and adjusted if needed, a present value of a mean usage of the memory bandwidth by the multiple processor units being determined, and, if this present value is outside the permissible range, the values of the usable memory bandwidth are adjusted for at least a part of the multiple processor units.