Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: A compound of Formula I is disclosed which is useful as an emitter in an OLED.

Abstract: Provided herein are battery packs for electric vehicles. A battery pack can include a housing having cavities. The battery pack can include electrode structures having a first tab terminal and a second tab terminal. A cover can be disposed over the housing. The cover can include first junction connectors extending between a first surface of the cover and a second surface of the cover. The first tab terminal of each electrode structure can be welded to respective first junction connectors.

Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: Techniques for providing a virtual touch screen are described. An example of a computing device with a virtual touch screen includes a projector to project a user interface image onto a touch surface, and a depth camera to generate a depth image representing objects in a vicinity of the user interface image, and a touch mask generator. The computing device also includes a touch detection module to analyze the touch mask to detect touch events. The touch detection module is configured to identify a finger in the touch mask, identify a centroid region of the finger and compute a distance of the centroid region from a touch surface, and compare the distance to a threshold distance to identify a touch event.

Abstract: A mechanism is described for facilitating deep learning inference acceleration in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to compare a current input value associated with a layer of a plurality of layers of a neural network to a cached input value associated with the layer. The one or more processors are further to import the cached input value for the layer for further processing within the neural network, if the current input value and the cached input value are equal.

Abstract: The disclosure provides an information processing method and device. In one embodiment, an information processing method comprises receiving a request for generating questions inputted by a user, the request for generating questions includes a to-be-learned knowledge point; acquiring, from a knowledge graph for questions, a node path including a target node indicating the to-be-learned knowledge point, the nodes in the knowledge graph for questions indicating question-answering steps of existing questions, knowledge points tested in the question-answering steps, and questioning styles corresponding to the question-answering steps; and generating questions required by the user according to question-answering steps, knowledge points tested in the question-answering steps, and questioning styles corresponding to the question-answering steps indicated by nodes on the node path. The present disclosure enables generation of new questions and facilitates the expansion of a question bank.

Abstract: A semiconductor device includes a P-type substrate, a first isolation region, a plurality of first N-well walls, and an electrostatic discharge (ESD) clamp circuit. The first isolation region is formed within the P-type substrate. The ESD clamp circuit is arranged to discharge ESD current upon detection of an ESD event, and includes a clamping component that is arranged to provide a discharge path for the ESD current. The clamping component is formed on a region wrapped in the first isolation layer and the first N-well walls.

Abstract: Provided herein are battery cells for battery packs in electric vehicles. The battery cell includes a housing defining an inner region, an electrolyte disposed within the inner region, and a gasket that couples a lid with the housing to seal the battery cell. The gasket can include an inner portion having an ingress point and an egress point. The inner portion can have disposed therein a thermocouple wire that extends through the inner portion, past the ingress point and past the egress point. The thermocouple wire can include a first lead, a second lead, and a third lead. The first, second, and third leads can be disposed within a common jacket between the ingress point and the egress point. A thermocouple sensor can be disposed in the inner region and be coupled with the first, second, and third leads of the thermocouple wire to provide sensed temperature information.

Abstract: A compound having a structure of Formula I, is provided. In Formula I, Z1 to Z16 are each CR or N; three consecutive ones of Z1 to Z16 within the same ring cannot be N; each R is independently a hydrogen or a substituent selected from a variety of substituents; at least one R includes and electron donor substituent; at least one R includes an electron acceptor substituent; and any two Rs on the same ring can be joined or fused together to form a ring. Organic light emitting devices, consumer products, formulations, and chemical structures containing the compounds are also disclosed.

Abstract: Semiconductor devices and fabrication methods are provided. A fabrication method includes: forming a source and drain material layer over a substrate; forming a mask layer over the source and drain material layer and including a first trench exposing a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer using the mask layer and the protective layer as an etch mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed; and removing the mask layer after the channel material layer and the gate structure are formed. The channel material layer is on the sidewalls and the bottom of the first trench and the second trench.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

Abstract: A compound of Formula I useful as an emitter in OLED is disclosed.

Abstract: A brain mapping system includes a brain signal acquisition device for collecting brain signals corresponding to different locations of the brain, a stimulator for generating a stimulus based upon a pseudorandom sequence, and a processor for segmenting the brain signals into a plurality of epochs and correlating features extracted from the epochs with the pseudorandom sequence to generate correlation functions, wherein a brain map is constructed by the correlation functions.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: An apparatus for producing 3D point-cloud model of physical objects includes a rotatable platform (11), multiple patterns asymmetrically arranged on the rotatable platform (11), a background curtain (13), and an image capturing unit (12) arranged facing toward the background curtain (13). A producing method includes: placing an object (2) to be scanned on the rotatable platform (11); setting a capturing amount during one-time rotation operation; controlling the rotatable platform (11) to perform the rotation operation, and controlling the image capturing unit (12) to capture corresponding images during the rotation operation according to the capturing amount, wherein each image includes the entire object (2) and multiple of the patterns, and records corresponding global coordinates; and, performing matching on multiple features of each of the images, and constructing a 3D point-cloud model of the object (2) according to a matching result of the features and the global coordinates of each of the images.

Abstract: Examples disclosed herein relate to application testing. The examples may enable identifying a set of tests for testing an application and identifying a set of attributes associated with a particular test of the set of tests. The set of attributes may comprise an average execution duration of the particular test, a last execution time of the particular test, and a last execution status of the particular test. The examples may further enable determining attribute scores associated with individual attributes of the set of attributes and obtaining user-defined weights associated with the individual attributes. The examples may further enable determining a test score associated with the particular test based on the attribute scores and the user-defined weights associated with the individual attributes. The set of tests may be sorted based on the test score associated with the particular test. The sorted set of tests may be executed.