Abstract: A memory circuit includes an operational amplifier configured to generate a bias voltage at an output terminal responsive to reference and feedback voltages received at respective first and second input terminals, a first NMOS device including a gate coupled to the output terminal of the operational amplifier, a second NMOS device including a gate coupled to a source terminal of the first NMOS device and a source terminal coupled to the second input terminal of the operational amplifier, a resistive device coupled between the source terminal of the second NMOS device and a power reference node, a third NMOS device including a gate coupled to the output terminal of the operational amplifier, a fourth NMOS device including a gate coupled to a source terminal of the third NMOS device, and a resistance-based memory device coupled between a source terminal of the fourth NMOS device and the power reference node.

Abstract: An electronic device is provided. The electronic device includes a bracket, a supporting member, a fastener and a processor module. The bracket includes a slot. In a fixed state, the fastener is adapted to affix the supporting member in the slot. In an adjustment state, the supporting member is adapted to be slid relative to the slot. The supporting member is connected to the processor module to restrict the processor module.

Abstract: A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: In some examples, a display device includes a panel, a scaler circuit, and a backlight control circuit. In some examples, the scaler circuit receives a panel identification from the panel and determines a backlight module driving configuration based on the panel identification. In some examples, the backlight control circuit receives the backlight module driving configuration from the scaler circuit and controls a backlight for the panel based on the backlight module driving configuration.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

Abstract: In some examples, a method includes dividing, by a first display device, video data into multiple buffers corresponding to regions of the video data. In some examples, the method includes receiving, by the first display device, an indicator from a second display device. In some examples, the method includes controlling, by the first display device, color processing of data of a first buffer of the multiple buffers based on the indicator to coordinate with the second display device.

Abstract: In some examples, a computing device includes a first video interface for a first monitor, a second video interface for a second monitor, and a processor. In some examples, the processor obtains a first monitor identification from the first monitor and obtains a second monitor identification from the second monitor. In some examples, the processor sends the first monitor identification and the second monitor identification to a color profile server. In some examples, the processor receives a first color profile and a second color profile from the color profile server. In some examples, the processor causes the first color profile and the second color profile to install on the computing device.

Abstract: This disclosure is directed to a case of an electronic device having a box, an elastic arm, a first fastening structure, a second fastening structure, and a magnet. The box has a first housing and a second housing closed with the first housing. The elastic arm is arranged in the first housing, the elastic arm is located at one side of the first housing, and at least a portion of the elastic arm is extended beyond an edge of the first housing. The first fastening structure is disposed on the elastic arm and located beyond the edge of the first housing. The second fastening structure is arranged on an internal surface at one side of the second housing, and the first fastening structure and the second fastening structure are buckled with each other. The magnet is arranged on the spring arm.

Abstract: A motor is provided and driven by two phase. The first and second control signals have a phase difference of 90 degrees and are configured to control the first and second driving units, respectively, and the first and second control signals drive the first and second coil sets, respectively. Each of the first and second poles of the permanent magnet occupies a mechanical angle of 360/2n degrees of the permanent magnet, respectively, and n is 1 or 3. The four sets of the coils of the stator are equally located on the stator, each set of the coil occupies a mechanical angle of 360/2m degrees of the stator, any two sets of the coils adjacent to each other are separated by a mechanical angle of 90?(360/2m) degrees, and m is 3 or 2, wherein m corresponds to 2 when n is 1, m corresponds to 3 when n is 3.

Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

Abstract: A direct memory access device has a first channel combination/separation unit, a second channel combination/separation unit and a data processing device. The first channel combination/separation unit selectively combines/separates channels of data received by the direct memory access device. The second channel combination/separation unit selectively combines/separates channels of data processed by the data processing device. The data are then output by the direct memory access device. The data processing device receives a data output by the first channel combination/separation unit. The data processing device is used to selectively perform at least one of amplification/down-scale process, data bit number adjustment process and shifting process on its received data, and output the data to the second channel combination/separation unit. A sequence and each number of the above-mentioned multiple processes are determined by control selection commands.

Abstract: A motor is provided and driven by two phase. The first and second control signals have a phase difference of 90 degrees and are configured to control the first and second driving units, respectively, and the first and second control signals drive the first and second coil sets, respectively. Each of the first and second poles of the permanent magnet occupies a mechanical angle of 360/2n degrees of the permanent magnet, respectively, and n is 1 or 3. The four sets of the coils of the stator are equally located on the stator, each set of the coil occupies a mechanical angle of 360/2m degrees of the stator, any two sets of the coils adjacent to each other are separated by a mechanical angle of 90?(360/2m) degrees, and m is 3 or 2, wherein m corresponds to 2 when n is 1, m corresponds to 3 when n is 3.

Abstract: A power supply system with current sharing includes a current sharing bus, a plurality of power supply units, and a plurality of controllers. The power supply units are connected to each other through the current sharing bus. Each power supply unit provides a current sharing signal value to the current sharing bus, and provides an output current to a load. Each controller receives current sharing signal values provided from other power supply units and current signal values corresponding to the output currents. When determining that the current signal value is less than a reference current sharing signal value, the controller increases an output voltage of the power supply unit to increase the output current. Otherwise, the controller decreases the output voltage to decrease the output current so that so that the output currents of the power supply units are shared to supply power to the load.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, the signal value of the first driving signal gradually decreases until being equal to the signal value of the second driving signal. Wherein the signal value of the first driving signal non-linearly decreases, the signal value of the second driving signal is an unchanged value. Wherein, the first time period and the second time period are adjusted for a different fan but the sum of the first time period and the second time period is always the same. A fan is also disclosed.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.