Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.

Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.

Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.