Abstract: A grinding machine tool for reducing hotness of a casing, includes a casing and a drive assembly. The casing is divided into a head and a body; includes casing parts; includes an air inlet provided on the body and an air outlet provided on a side of the head; and forms a motor cover on the head, and the motor cover does not contact the casing parts to form an airflow passage in the casing. The drive assembly includes a circuit board, a motor placed into the motor cover, and an airflow generating member rotating synchronously with the motor. When the airflow generating member rotates, it generates a first heat dissipation airflow passing through the airflow passage and dissipating heat of the circuit board and the head, and a second heat dissipation airflow dissipating heat on a side of the motor facing the airflow generating member.

Abstract: An air guider disposed in a grinding machine tool. The grinding machine tool comprises a casing and a motor disposed in the casing. The casing comprises a head for disposing the motor and a body formed with at least one air inlet. The air guider comprises a main body, and an ascending diversion portion integrally formed with the main body, the main body is disposed at a junction between the head and the body, the ascending diversion portion comprises a main guide surface to guide a first heat dissipation airflow entering from the air inlet to flow toward a top of the motor, and two auxiliary guide surfaces respectively disposed on two sides of the main guide surface to generate a second heat dissipation airflow.

Abstract: A semiconductor device according to one embodiment includes a substrate, a wiring layer provided on the substrate and including source lines, a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the wiring layer, a cell film provided in the stacked body, a semiconductor film facing the cell film in the stacked body, and a diffusion film being in contact with the source lines in the wiring layer and being in contact with the semiconductor film in the stacked body. The diffusion film includes impurities and a top end portion of the diffusion film is at a higher position than a lowermost conductive layer among the conductive layers.

Abstract: A transmission control method is disclosed. The transmission control method includes: sending, by a base station, downlink data to a terminal at a high frequency when detecting that the downlink data needs to be transmitted at the high frequency; and sending, by the terminal to the base station at the high frequency, control information used for assisting the base station in improving transmission quality of the high frequency downlink data, so that the base station controls a transmission process of the high frequency downlink data according to the control information. Embodiments of the present invention further disclose a base station and a terminal. By means of the present invention, a terminal can rapidly feed back control information at a high frequency in a process in which downlink data is transmitted at a high frequency, and a feedback time is short.

Abstract: A transmission control method is disclosed. The transmission control method includes: sending, by a base station, downlink data to a terminal at a high frequency when detecting that the downlink data needs to be transmitted at the high frequency; and sending, by the terminal to the base station at the high frequency, control information used for assisting the base station in improving transmission quality of the high frequency downlink data, so that the base station controls a transmission process of the high frequency downlink data according to the control information. Embodiments of the present invention further disclose a base station and a terminal. By means of the present invention, a terminal can rapidly feed back control information at a high frequency in a process in which downlink data is transmitted at a high frequency, and a feedback time is short.

Abstract: A cord winding mechanism for an electrically powered device such as a vacuum cleaner. The cord winding mechanism may be used with a device having an electric motor. The mechanism may include a cord receiving member for receiving a cord. The cord receiving member may define an interior space and have an axis. The mechanism may include a biasing member that may transmit a rotational force to the cord receiving member to rotate the cord receiving member about the axis. The mechanism may include a retention member that may selectively prevent the cord receiving member from rotating under the rotational force of the biasing member. The cord receiving member may be adapted to receive at least part of the motor inside the interior space of the cord receiving member. The mechanism may include ventilation openings for providing ventilation An electric motor assembly may include the mechanism and a motor. An electric appliance may include a housing and the assembly.

Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.

Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.

Abstract: A buffer manager provides address information for reading and writing data to an SDRAM. The address information is translated from a flat memory address space into an SDRAM address space. The buffer manager operates based upon a first clock and the SDRAM operates based upon a second clock. Accordingly, a synchronization circuit synchronizes the data. The translation of address information occurs simultaneously with the synchronization of data.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end address. To write data to a buffer, the buffer manager provides a start address and burst size to an address translator. The address translator converts the start address and the burst size to SDRAM memory address locations. The start and end address of each buffer is mapped to a different bank in the SDRAM memory.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.

Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.