Abstract: A gene regulatory relationship detection model training method performed by an electronic device, and relate to the field of biology technologies. The gene regulatory relationship detection model training method includes: obtaining material group data of a plurality of sample genes and an annotated regulatory relationship between at least one sample gene pair; determining a predicted probability that a regulatory relationship exists between each two sample genes among the plurality of sample genes by using a neural network model based on the material group data of the plurality of sample genes; and training the neural network model to obtain a gene regulatory relationship detection model, based on the annotated regulatory relationship between the at least one sample gene pair and the predicted probability between each two sample genes.

Abstract: The present disclosure provides a method for separating a neural crest derived cell from peripheral blood. In the present disclosure, a mononuclear cell is separated from the peripheral blood and then directly cultured, thereby maximizing use of a neural crest stem cell with a differentiation potential to avoid loss of the neural crest stem cell. In the method of the present disclosure, a sample to be separated is derived from the peripheral blood. The method shows less trauma and low cost. Most importantly, compared to extracting the neural crest derived cell from tissues, the neural crest derived cell extracted from the peripheral blood can be used clinically as a type of biomarker.

Abstract: A method for the reaction of an isatin and cyclopropenone compound at low catalytic amount. In the presence of an amine compound and phosphite, the isatin and cyclopropenone are reacted in an organic solvent using a silicon amino rare earth compound as a catalyst to synthesize pyrano[2,3-b]indol-2-one compounds. In the reaction above, the amount of catalyst is few, and noble metal is not needed for catalysis. The present method can achieve preparation of the pyrano[2,3]indol-2-one compound efficiently and simply.

Abstract: A system and method for defense against cache timing channel attacks using cache management hardware is provided. Sensitive information leakage is a growing security concern exacerbated by shared hardware structures in computer processors. Recent studies have shown how adversaries can exploit cache timing channel attacks to exfiltrate secret information. To effectively guard computing systems against such attacks, embodiments disclosed herein provide practical defense techniques that are readily deployable and introduce only minimal performance overhead. In this regard, a new protection framework against cache timing channel attacks is provided herein by leveraging commercial off-the-shelf (COTS) hardware support in processor caches, including last level caches (LLC), for cache monitoring and partitioning. This framework applies signal processing techniques on per-domain cache occupancy data to identify suspicious application contexts.

Abstract: A frequency divider circuit is provided. The frequency divider circuit processes multiple input clocks. The frequency divider circuit includes a frequency dividing circuit and a retiming circuit. The frequency dividing circuit generates an intermediate clock according to a first subgroup of the input clocks. The retiming circuit generates multiple output clocks according to a second subgroup of the input clocks and the intermediate clock. The periods of the input clocks are all a first period, and the periods of the output clocks are all a second period. The first period is smaller than the second period. The frequency dividing circuit and the retiming circuit operate according to a mode control signal which determines a ratio of the first period to the second period.

Abstract: A frequency divider circuit is provided. The frequency divider circuit processes multiple input clocks. The frequency divider circuit includes a frequency dividing circuit and a retiming circuit. The frequency dividing circuit generates an intermediate clock according to a first subgroup of the input clocks. The retiming circuit generates multiple output clocks according to a second subgroup of the input clocks and the intermediate clock. The periods of the input clocks are all a first period, and the periods of the output clocks are all a second period. The first period is smaller than the second period. The frequency dividing circuit and the retiming circuit operate according to a mode control signal which determines a ratio of the first period to the second period.

Abstract: A system and method for defense against cache timing channel attacks using cache management hardware is provided. Sensitive information leakage is a growing security concern exacerbated by shared hardware structures in computer processors. Recent studies have shown how adversaries can exploit cache timing channel attacks to exfiltrate secret information. To effectively guard computing systems against such attacks, embodiments disclosed herein provide practical defense techniques that are readily deployable and introduce only minimal performance overhead. In this regard, a new protection framework against cache timing channel attacks is provided herein by leveraging commercial off-the-shelf (COTS) hardware support in processor caches, including last level caches (LLC), for cache monitoring and partitioning. This framework applies signal processing techniques on per-domain cache occupancy data to identify suspicious application contexts.