Patents by Inventor Fan-yi Hsu
Fan-yi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8361855Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: October 4, 2011Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Ouyang Hui
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Publication number: 20120322246Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung WANG, Hsien-Chin LIN, Yuan-Ching PENG, Chia-Pin LIN, Fan-Yi HSU, Ya-Jou HSIEH
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Patent number: 8329546Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.Type: GrantFiled: August 31, 2010Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Hui Ouyang, Ming-Jie Huang, Shin Hsien Liao
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Publication number: 20120248550Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Chia-Pin LIN, Sheng-Hsiung WANG, Fan-Yi HSU, Chun-Liang TAI
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Patent number: 8173504Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.Type: GrantFiled: April 12, 2010Date of Patent: May 8, 2012Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Hui Ouyang, Chi-Ming Yang
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Publication number: 20120049247Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Hui Ouyang, Ming-Jie Huang, Shin Hsien Liao
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Publication number: 20120018817Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: October 4, 2011Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt YEH, Yi-Chen HUANG, Fan-Yi HSU, Ouyang HUI
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Patent number: 8048733Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: April 9, 2010Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Ouyang Hui
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Publication number: 20110250725Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt YEH, Fan-Yi HSU, Shun Wu LIN, Hui OUYANG, Chi-Ming YANG
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Publication number: 20110086502Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: April 9, 2010Publication date: April 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt YEH, Yi-Chen HUANG, Fan-Yi HSU, Ouyang HUI
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Publication number: 20100124823Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt Yeh, Fan-Yi Hsu, Shun Wu Lin, Shu-Yuan Ku, Hui Ouyang
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Patent number: 6025588Abstract: A potentiometer includes a shaft, a base including a printed circuit board on which are fixedly mounted a light emitter and a light receiver arranged opposite to and spaced from the light emitter, the light emitter being supplied with steady voltage to emit light and provide working voltage to the light receiver, a circular seat formed with an opening and fixedly mounted on an upper end of the shaft, a plastic film arranged on an outer edge of the opening and disposed between the light emitter and the light receiver, the plastic film being provided two end portions which are opaque and an intermediate portion which decreases in transparency from one side to another side thereof, and a cover fixedly mounted on the base to enclose the circular seat, whereby the potentiometer is of high sensitivity, durable in use, low in cost, easily converted from a conventional rheostat and fit for mass production.Type: GrantFiled: September 21, 1998Date of Patent: February 15, 2000Assignee: Anko Electronics Co., Ltd.Inventor: Fan-Yi Hsu
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Patent number: 5805141Abstract: A joystick direction control means mainly including a variable resistance, a mounting seat assembled onto a resistance adjusting rod of the variable resistance and being fixed thereto by lugs projecting from the variable resistance and engaging with four comers of the mounting seat, and a mounting board assembled to the mounting seat by extending a central shaft of the mounting seat and two retaining wings at two sides of the central shaft through a receiving hole on the mounting board and turning the mounting board about the central shaft by 90 degrees, so that the whole joystick direction control means can be quickly assembled with the mounting board properly tightened to the mounting seat.Type: GrantFiled: May 29, 1997Date of Patent: September 8, 1998Assignee: Anko Electronic Co., Ltd.Inventor: Fan-yi Hsu
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Patent number: 5640177Abstract: An optical analog rocker in which mechanical movements of a manipulated control rod of the rocker are converted into electronic signals by means of an infrared emitter and an infrared receiver. The infrared receiver shifts relative to the infrared emitter when the control rod is swayed in different directions and thereby, changes the distance between it and the infrared emitter. The changing distance causes the infrared receiver to generate light-sensitive signals of different high or low linear voltage and current. The signals are received by a game interface card and are correctly sent to a computer. With these arrangements, the disadvantages associated with a worn variable resistance contact included in a rocker, such as poor contact condition and unstable signal output can be avoided.Type: GrantFiled: March 15, 1995Date of Patent: June 17, 1997Assignee: Anko Electronic Co., Ltd.Inventor: Fan-yi Hsu