Patents by Inventor Fan Yin
Fan Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387112Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 11804488Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: July 20, 2022Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20230214677Abstract: An auditing system executes a first machine learning model on a first computing platform using input data to generate first output data. The auditing system executes a second machine learning model on a second computing platform using the input data to generate second output data. The second machine learning model is generated by migrating the first machine learning model to the second computing platform. The auditing system determines one or more performance metrics based on comparing the first output data to the second output data. The auditing system classifies, based on the one or more performance metrics, the second machine learning model with a classification. The classification comprises a passing classification or a failing classification. The auditing system causes the second model to be modified responsive to classifying the second model with a failing classification.Type: ApplicationFiled: December 29, 2022Publication date: July 6, 2023Inventors: Royce ALFRED, Fan YIN
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Publication number: 20230088743Abstract: An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Supratim Pal, Chandra Gurram, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy R. Bauer, Vikranth Vemulapalli, Wei-Yu Chen
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Publication number: 20230056759Abstract: The present disclosure relates to systems, methods, and computer-readable media for receiving usage data for a virtual device (or other virtual service), analyzing the usage data to determine a usage bucket characteristic of usage of the virtual device over a period of time, and determining a usage score for the virtual device. The systems described herein further involve causing a deployment of the virtual device to be upgraded, downgraded, or otherwise modified based on the usage bucket and associated usage score. The features and functionalities described herein can provide an efficient mechanism for administrating a tenant deployment as well as implementing a more efficient utilization of cloud computing resources for a variety of virtual services.Type: ApplicationFiled: December 6, 2021Publication date: February 23, 2023Inventors: Hu LU, XiWen YUE, Lingxiao HANG, Haiyang WANG, Ankit SRIVASTAVA, Fan YIN, Naga Venkata Rajagopal RAMADUGU, Nandita SHARMA, Jyh-Han LIN, Sandeep PATNAIK
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Publication number: 20220367664Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.Type: ApplicationFiled: July 21, 2022Publication date: November 17, 2022Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
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Publication number: 20220359505Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 11437484Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.Type: GrantFiled: April 22, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
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Patent number: 11398477Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: November 30, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 11291135Abstract: A chassis includes a receiving member, a bracket, and a sliding assembly. The bracket is configured to be mounted in a cabinet. The sliding assembly is configured to slidably mount the receiving member on the bracket.Type: GrantFiled: November 18, 2020Date of Patent: March 29, 2022Assignee: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO., LTD.Inventors: Han-Yu Li, Xiang-Hui Zeng, Fan-Yin Meng
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Patent number: 11251079Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.Type: GrantFiled: June 3, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
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Publication number: 20220015257Abstract: A chassis includes a receiving member, a bracket, and a sliding assembly. The bracket is configured to be mounted in a cabinet. The sliding assembly is configured to slidably mount the receiving member on the bracket.Type: ApplicationFiled: November 18, 2020Publication date: January 13, 2022Inventors: HAN-YU LI, XIANG-HUI ZENG, FAN-YIN MENG
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Publication number: 20210327742Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
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Patent number: 11049756Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.Type: GrantFiled: February 4, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Huei Chiu, Tsung Fan Yin, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu
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Publication number: 20210111176Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: November 30, 2020Publication date: April 15, 2021Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Patent number: 10854603Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: GrantFiled: May 29, 2019Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
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Publication number: 20200303255Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.Type: ApplicationFiled: June 3, 2020Publication date: September 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hua-Li HUNG, Chih-Lun LU, Hsu-Yu HUANG, Tsung-Fan YIN, Ying-Ting HSIA, Yi-Wei CHIU, Li-Te HSU
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Patent number: 10721833Abstract: A server which can be connected from the back or from the front includes a case and a compute node disposed in the case. The case has a front board and an opposite rear board. The compute node has a plurality of ports for connecting to external cables. The front board has a first opening defined thereon, the rear board has a second opening defined thereon, and the second opening faces the first opening. The compute node is capable of being loaded into the case facing a first direction, such that the plurality of ports are exposed from the first opening. The compute node is also capable of being loaded into the case facing a second direction, opposite to the first direction, such that the plurality of ports are exposed from the second opening.Type: GrantFiled: May 14, 2019Date of Patent: July 21, 2020Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) CO., LTD.Inventors: Fan-Yin Meng, Han-Yu Li, Ge Liu, Cheng Yang, Xin Chen
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Patent number: 10692762Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.Type: GrantFiled: September 10, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
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Publication number: 20200006334Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.Type: ApplicationFiled: May 29, 2019Publication date: January 2, 2020Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu