Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.

Abstract: A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed on the substrate. The inter-level dielectric layer is disposed between the plurality of interconnect layers. The last layer of the interconnect layers comprises an I/O pad, a first pad and a second pad. A first diode and a second diode are disposed on the last layer of the inter-level dielectric layer, wherein the first diode electrically connects to the I/O pad and the first pad and the second diode electrically connects to the I/O pad and the second pad.