Patents by Inventor Fang An

Fang An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190393932
    Abstract: A multi-input multi-output (MIMO) Bluetooth module with effectively suppressed mutual interference is disclosed. The MIMO Bluetooth module has multiple Bluetooth transceivers which operate in a synchronized transmission mode, in which no Bluetooth transceiver is permitted to transmit data when any of the Bluetooth transceivers are receiving data.
    Type: Application
    Filed: May 24, 2019
    Publication date: December 26, 2019
    Inventors: Chien-Fang HSU, Li-Chun KO
  • Publication number: 20190393080
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 26, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • Publication number: 20190389689
    Abstract: Methods and systems for controlling elevator systems are provided. The methods include receiving inputs from at least one interactive input device, wherein the inputs include elevator call requests, tracking one or more people located within a monitored area using at least one sensor, assigning elevator assignments to the one or more people based on at least one of the inputs from the at least one interactive input device and a grouping algorithm based on the tracking of the one or more people, and scheduling operation of at least one elevator car based on the elevator assignments.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 26, 2019
    Inventors: Zhen Jia, Hui Fang, Arthur Hsu, Alan Matthew Finn, Luca F. Bertuccelli
  • Patent number: 10513415
    Abstract: A passenger conveyance system includes a depth-sensing sensor for capturing depth map data of objects within a field of view adjacent a passenger conveyance door. A processing module in communication with the depth-sensing sensor to receive the depth map data, the processing module uses the depth map data to track an object and calculate passenger data associated with the tracked object, and a passenger conveyance controller to receive the passenger data from the processing module, wherein the passenger conveyance controller controls a passenger conveyance dispatch control function in response to the passenger data.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 24, 2019
    Assignee: Otis Elevator Company
    Inventors: Hui Fang, Arthur Hsu, Alan Matthew Finn, Zhen Jia
  • Patent number: 10515950
    Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming a first doped well within the substrate, and forming a second doped well within the substrate. The second doped well is non-contiguous with the first doped well. The method further includes depositing a dielectric layer over the substrate, and forming a first resistor element within the dielectric layer. The first resistor element is aligned with the first doped well. The method further includes forming a second resistor element within the dielectric layer. The second resistor element being aligned with the second doped well.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lung Tung, Min-Chang Liang, Fang Chen
  • Patent number: 10514865
    Abstract: Techniques for a managing concurrent I/Os in a file system may include receiving a sequence of conflicting I/O lists of write data stored in a cache, the sequence specifying a sequential order in which the I/O lists are to be flushed to a file stored on non-volatile storage; determining a first I/O list of the sequence having a conflict with a second I/O list of the sequence, wherein the conflict between the first I/O list and the second I/O list is a first common block written to by both the first and second I/O lists; and performing first processing that modifies the first I/O list and the second I/O list to remove the conflict.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 24, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ivan Bassov, Hao Fang
  • Patent number: 10515961
    Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 10513605
    Abstract: The present invention relates to a halogen-free epoxy resin composition, a prepreg and a laminate containing the same. The halogen-free epoxy resin composition comprises 60 parts by weight of epoxy resin, from 15 to 28 parts by weight of benzoxazine resin, and from 10 to 20 parts by weight of styrene-maleic anhydride. The present invention discloses using from 15 to 28 parts by weight of benzoxazine resin and from 10 to 20 parts by weight of styrene-maleic anhydride to cure 60 parts by weight of epoxy resin, to ensure the Df stability of prepregs at different curing temperature conditions while maintaining low dielectric constant and low dielectric loss. The prepregs and laminates prepared from the resin composition have comprehensive performances, such as low dielectric constant, low dielectric loss, excellent flame retardancy, heat resistance, cohesiveness, low water absorption and moisture resistance, and are suitable for use in halogen-free multilayer circuit boards.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: December 24, 2019
    Assignee: SHENGYI TECHNOLOGY CO., LTD.
    Inventors: Hui Li, Kehong Fang, Yongjing Xu
  • Patent number: 10516288
    Abstract: Each wireless charging device of the wireless charging system has a Bluetooth module for detecting signal strength between the wireless charging device and an electronic device. The signal strength information is shared among the wireless charging devices by their data transceiver units. An analysis module of each wireless charging device automatically determines one wireless charging device having the best connection, and a decision module of the determined wireless charging device transmits a charging permit to the electronic device. Cross connection of the electronic device to multiple wireless charging devices is therefore avoided.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 24, 2019
    Assignees: NEWVASTEK CO., LTD., GUNITECH CORP.
    Inventors: Ming-Liang Fang, Chih-Hao Chuang, Huan-Ruei Shiu
  • Patent number: 10515861
    Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng
  • Patent number: 10515963
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Patent number: 10514894
    Abstract: A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 24, 2019
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Hongzhen Fang, Yuejun Zhang
  • Patent number: 10515090
    Abstract: A system and method for processing raw transaction records received from multiple data sources. The system and method receive multiple raw transaction records from multiple data sources. Transaction pair records are generated from the raw transaction records. Location and entity fields including raw information are identified from the transaction pair records. The raw location and entity information is resolved to generate resolved location and entity information capable of aggregation and further processing, such as the deriving of analytics.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 24, 2019
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Vahram Avagyan, Andrea Fang, Robert J. Prior, Vipul V. Shah, Jonathan Scott Hajek
  • Patent number: 10515809
    Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
  • Patent number: 10513416
    Abstract: An passenger conveyance system includes a depth-sensing sensor within a passenger conveyance enclosure for capturing depth map data of objects within a field of view that includes a passenger conveyance door. A processing module is in communication with the depth-sensing sensor to receive the depth map data, the processing module uses the depth map data to track an object and calculate passenger data associated with the tracked object. a passenger conveyance controller receives the passenger data from the processing module to control operation of a passenger conveyance door in response to the passenger data.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 24, 2019
    Assignee: Otis Elevator Company
    Inventors: Hui Fang, Arthur Hsu, Alan Matthew Finn, Zhen Jia
  • Publication number: 20190386267
    Abstract: Disclosed is a battery sleeve case for a portable electronic device (e.g., laptop computer or electronic tablet device) that includes an elastic polymer frame structure that extends around a perimeter of the sleeve to provide cushioning or padding to the sides of the device. Front and back face side panels are attached to opposing sides of the frame structure, via stitching or some other suitable means. The frame structure may be formed of injected molded ethylene vinyl acetate (EVA) or other suitable material. The side panels may be laminated with fabric, with a front face side panel being flexible and cushioned and including one or more access flaps. The back face side panel includes a rechargeable battery housed within a battery compartment defined by a semi rigid outer panel, which may be formed of compression molded EVA or other suitable material. The rechargeable battery is electrically coupled to external and internal electrical interfaces.
    Type: Application
    Filed: January 10, 2019
    Publication date: December 19, 2019
    Applicant: Incase Designs Corp.
    Inventors: Kenji Okada, Hyun Hong, Dominique Velasco Fonacier, Kevin I-Feng Fang
  • Publication number: 20190384466
    Abstract: Key content of a plurality of segments of a media presentation can be identified by analyzing the plurality of segments of the media presentation. Comments pertaining to the media presentation can be scanned, and to which of the plurality of segments of the media presentation each comment pertains can be determined. Links between the comments and particular segments of the media presentation to which the comments are directed can be created, wherein the links are user selectable to jump to the particular segments of the media presentation. The comments with the links to the particular segments of the media presentation to which the comments are directed can be presented in a user interface presented on a display.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Inventors: Fang Lu, Paul R. Bastide, Robert E. Loredo, Matthew E. Broomhall
  • Publication number: 20190380945
    Abstract: A method of degrading bilirubin in skin is provided. The method involves identifying a target portion of skin where a reduction in bilirubin level is desired, and applying a vitamin B3-containing, low-pH composition to the target portion of skin during a treatment period. The composition contains an effective amount of a vitamin B3 compound, has a pH of less than 5.0, and reduces bilirubin level in the target portion of skin during the treatment period. The amount of vitamin B3 compound and the pH of the composition may be selected to provide a synergistic reduction in bilirubin level, as compared to the reduction in bilirubin level provided by the same composition at a neutral pH.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventors: Tomohiro HAKOZAKI, Bin FANG DEYER
  • Publication number: 20190386000
    Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.
    Type: Application
    Filed: April 29, 2019
    Publication date: December 19, 2019
    Inventors: Fang Chen, Jhon Jhy Liaw
  • Patent number: D870947
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 24, 2019
    Assignee: Hangzhou Amplesun Solar Technology Co., Ltd.
    Inventors: Hongchao Zhang, Fang Hao, Hongxin Zeng, Liping Zhou