Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: The present application discloses a processing method, device, terminal and apparatus for partial bandwidth deactivation timer, including: receiving an instruction related to the uplink transmission sent by the network side; starting or restarting the partial bandwidth deactivation timer according to the received instruction. The present application clarifies the specific working mechanism of the partial bandwidth deactivation timer, so that the terminal and the base station can perform signaling and data transmission on the correct resources, thereby avoiding signaling and data transmission errors and resource waste.

Abstract: The present application relates to the field of communications, and in particular to a channel and/or signal transceiving method and apparatus. The method comprises: a network side configuring a first channel and/or a first signal, wherein the first channel and/or the first signal are/is used for indicating the receiving and/or sending of a second signal of at least one terminal group corresponding to at least one terminal; and the network side sending the first channel and/or the first signal to the at least one terminal, and the terminal receiving, on the basis of a manner indicated by the network side, the second signal sent by the network side, such that when the terminal is in an RRC-idle or RRC-inactive state, the network side can reduce, in the manner, the number of times that various types of messages are received by a terminal side.

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Abstract: A method for manufacturing a multi-functional fastener includes a preparing operation, a forming operation and a threading operation. The preparing operation prepares a metal blank cut from a length of a metal material. The forming operation is executed so that the metal blank forms a shank, a head, and a drilling portion connected to the shank. The threading operation is executed to roll the metal blank with a thread rolling set having two opposite rolling plates. Each rolling plate has slit grooves and convex units arranged in alternation. Each of the convex units has protrusions each situated between two adjacent slit grooves, which allows the threading operation to equip the shank of the metal blank with thread convolutions, slots formed between the thread convolutions for helping quick removal of chips, and main ribs formed between any two adjacent slots for increasing cutting efficiency.

Abstract: A screw includes a threaded shank and a head with a first surface. Communicating sockets formed in the first surface include a Pozi-type socket and a drive socket. The drive socket includes rounded portions, arched portions alternating with the rounded portions, and a conical portion connected to the rounded portions and the arched portions to define a first reference line and a second reference line parallel to a central axis of the head. The rounded portions are inclined outwardly from the first reference line, and the arched portions are inclined outwardly from the second reference line. Thus, a first room enclosed by the rounded portions and the arched portions increases gradually towards the first surface. By a combination of the above sockets, the head cooperates with different driving tools for delivering driving force efficiently and is more convenient to use.

Abstract: The embodiments of the present application provide a wakeup region update method and device for updating a wakeup region of a terminal. The method includes a terminal receiving a wakeup signal, the wakeup signal carrying a wakeup region indicator; and the terminal updating the wakeup region indicator of the terminal according to the wakeup region indicator carried by the wakeup signal received. The present application is adopted to achieve updating and maintenance of the wakeup region of the terminal.

Abstract: The present application provides a method and apparatus for configuring a transmission bandwidth, and a device, for accelerating an activation speed of a carrier/BWP, reducing waiting time of a UE, and saving power consumption of the UE. The method comprises: determining a first carrier/first BWP; and sending a PDCCH to a user terminal UE by means of a second carrier/second BWP, the PDCCH being used for bearing instruction information for activating the first carrier/first BWP and sending a reference signal over the first carrier/first BWP, so that the UE may activate the first carrier/first BWP and receive the reference signal, and the reference signal is used by the UE for performing channel measurement and synchronous tracking on the first carrier/first BWP.

Abstract: This invention discloses a practical method for landslide detection in large space, which comprises the following steps: image synthesis, ice and snow detection, removal of non-potential landslide area, detection of potential landslide area, feature calculation, landslide detection model construction and precision validation; this invention avoids radiometric correction and outlier by detecting landslide from synthetic image. That guarantees practical applicability of the proposal. Firstly, detecting potential landslides can avoid the imbalanced sample distribution issue between background objects and landslides when training the landslide detection model. The landslide is further detected by building a random forest model based on the spectral features and textural features of potential landslide pixels in different neighboring time domains. It fully considers the changes of objects in different time domains, and lays a foundation for efficient landslide extraction.

Abstract: Disclosed herein is a hydrogel wound dressing produced by the steps of a) providing an hydrophobic polyol which has six hydroxyl groups, b) providing an hydrophilic diisocyanate obtained by reacting a second diisocyanate with a hydrophilic polyether diol, c) reacting the hydrophobic polyol with the hydrophilic diisocyanate to obtain a first prepolymer which includes 3 to 6 isocyanate groups, d) partially crosslinking the first prepolymer using a crosslinking agent to obtain a second prepolymer, and e) subjecting the second prepolymer to an end-capping reaction with a silane-containing compound to obtain the hydrogel wound dressing.

Abstract: A light emitting diode (LED) display panel is provided. The LED display panel includes a printed circuit board (PCB), a flexible substrate disposed on the PCB, and a pixel array. The flexible substrate has a plurality of holes. The pixel array is formed by a first matrix circuit disposed on the flexible substrate, a second matrix circuit disposed on the PCB, and a plurality of LEDs disposed on the PCB, collectively defining a plurality of pixels. Each of the pixels comprises a corresponding one of the LEDs and pixel circuits formed by the first matrix circuit and the second matrix circuit. A projection of each of the LEDs correspondingly overlaps with a projection of one of the holes on the flexible substrate along an extending direction of the holes. A mosaic LED display panel may be formed by multiple LED display panel butted or tiled together.

Abstract: A liquid dressing includes a solvent and a film-forming polymer that is dissolved in the solvent and that is made by a process including: providing an alkoxy group-containing silicone resin which is obtained by subjecting an orthosilicate compound and an acidic aqueous solution to a hydrolysis and polymerization reaction; providing an isocyanate group-containing prepolymer which is obtained by reacting a diisocyanate compound with a hydrophilic polyether diol; and subjecting the alkoxy group-containing silicone resin and the isocyanate group-containing prepolymer to a polymerization reaction so as to obtain the film-forming polymer.

Abstract: A driving circuit for a display panel and including a receiving interface, a timing controller, a pulse width modulation controller and a line latch is disclosed. The receiving interface is configured to receive a first input signal, a second input signal and a link signal to generate a plurality of display data accordingly, wherein the first input signal and the second input signal are a pair of differential signals. The timing controller is configured to interpret the first input signal, the second input signal and the link signal to generate a trigger signal. The pulse width modulation controller is configured to perform pulse width modulation to generate a first output signal and a second output signal. The line latch is configured to hold the first and second output signals, and output the first and second output signals according to the trigger signal to drive the display panel.

Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.

Abstract: A random emulsification digital absolute quantitative analysis method includes: performing random emulsification processing on a system to be emulsified to obtain several isolated reaction zones or droplets; determining the total number and volume information of the various reaction zones or droplets, the presence of target molecules to be tested in the respective reaction zones or droplets, and the number of reaction zones or droplets which do not contain the target molecules by combining acquired target images comprising image regions corresponding to the amplified reaction zones or droplets, and analyzing the target images; and accurately calculating the volume information of the various reaction zones or droplets, the presence of the target molecules to be tested in the respective reaction zones or droplets, and the number of reaction zones or droplets which do not contain the target molecules, the total number of target molecules in a sample to be tested.

Abstract: Embodiments of the present application provide a method and a device for determining a power control offset for a PUCCH, for resolving the issue in which existing methods for determining a power control offset for a PUCCH are incompatible with new radio communications systems. The method comprises: determining the number of bits, OUCI, of first uplink control information (UCI) required to be transmitted on a PUCCH, and determining the number, NRE, of resource elements (RE) carrying the first UCI in the PUCCH; and determining, according to formula (I), an offset ?PUCCH_TF,c(i) for calculation of power control of the PUCCH, and g(OUCI/NRE) is a function having OUCI and NRE as variables thereof.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.