Abstract: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.

Abstract: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.

Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask.

Abstract: The invention comprises processes for determining and applying a deblurring filter that reduces inspection system distortion, of mask inspection images, by compensating for the non-uniform frequency response of the inspection system. In particular, an adaptive filter is determined empirically for an inspection system: one or more training images are obtained by the inspection system and the filter is determined from such images. In this way, the filter can adapt to the characteristics of each individual inspection system. An example adaptive filter, known as a Weiner filter, is determined and applied.

Abstract: An automated metrology recipe set up process is described for a manufacturing process, in which patterns to be formed on a device are defined using a design database. The design database is processed to produce a simulated image of a feature for use in a metrology tool for a measurement of the feature. The simulated image is supplied to the metrology tool, where it is used as a basis for alignment of the tool for the measurement. Other recipe data is combined with the simulated image to provide a fully automated metrology set up process.

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated.

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.

Abstract: Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.

Abstract: A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.

Abstract: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.

Abstract: A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.

Abstract: Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.

Abstract: The invention comprises processes for determining and applying a deblurring filter that reduces inspection system distortion, of mask inspection images, by compensating for the non-uniform frequency response of the inspection system. In particular, an adaptive filter is determined empirically for an inspection system: one or more training images are obtained by the inspection system and the filter is determined from such images. In this way, the filter can adapt to the characteristics of each individual inspection system. An example adaptive filter, known as a Weiner filter, is determined and applied.

Abstract: A two-dimensional yield map for a device, such as an integrated circuit, in a fabrication facility is computed and associated with layout data for the device in a hierarchical and/or instance-based layout file. The device has a layout including a pattern characterizable by a combination of members of a set of basis shapes. A set of basis pre-images include yield map data representing an interaction of respective members of the set of basis shapes with a defect model. A yield map for the pattern is created by combining basis pre-images corresponding to basis shapes in the combination of members that characterize the pattern to provide a combination result. The output may be displayed as a two dimensional map to an engineer performing yield analysis, or otherwise processed.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: Design geometry information from an area outside the area of interest (AOI) on a mask can be combined with inspection information from the AOI to facilitate an accurate, simulated wafer image. The design geometry information can be easily generated or accessed, thereby ensuring an uninterrupted inspection process and minimizing the associated storage costs for the simulation process. The design geometry information can be pseudo design geometry information or actual design geometry information.

Abstract: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication.

Abstract: A monitoring method for photoresist regeneration, a process and a system for the same are provided. In the photoresist regeneration process of the invention, the solid content and viscosity of photoresist are adjusted by condensation under reduced pressure or dilution with photoresist thinner until the final solid content and viscosity reach the predetermined values thereof obtained through the quantification equation of the invention and then the waste photoresist is caused to pass through filters for removing pollution particles contained therein, such that the regenerated photoresist is acquired.