Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract: A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

Abstract: A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.

Abstract: A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.

Abstract: A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure.

Abstract: A method for controlling a critical dimension in an etched structure comprises the steps of: forming a hard mask above a substrate, measuring a critical dimension of the hard mask, and using the measured hard mask critical dimension to control a critical dimension trim operation performed on a circuit trace above the substrate.

Abstract: A method for forming a patterned mask layer within a microelectronic product employs a sequential linewidth measurement and trimming of a patterned mask layer to form multiply trimmed patterned mask layer. The sequential linewidth measurement and trimming employs at least two linewidth measurements and two patterned mask layer trimmings to provide a multiply trimmed patterned mask layer having an actual linewidth intended to be near a pre-determined target linewidth.

Abstract: A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

Abstract: A process sequence for forming a MOSFET device featuring a high k gate insulator layer, wherein the use of the high k gate insulator layer requires no additional photolithographic procedures, has been developed. After deposition of a high k gate insulator layer followed by the definition of an overlying conductive gate structure, an insulator layer is deposited. An anisotropic dry etch procedure is then employed to first define offset insulator spacers on the sides of the conductive gate structure, then to selectively remove the unwanted portions of the high k gate insulator layer. The use of the high k gate insulator layer provides a thin gate insulator layer with less risk of leakage when compared to counterpart gate insulator layers such as silicon dioxide, while the integration of the definition of the offset insulator spacer step and of the high k gate layer removal procedure, results in fabrication cost savings.

Abstract: A method for forming an offset spacer adjacent a CMOS gate structure with improved critical dimension control including providing a substrate that has a gate structure; forming at least one oxide layer over the substrate; forming at least one nitride layer over the at least one oxide layer; dry etching the at least one nitride layer in a first dry etching process to expose a first portion of the at least one oxide layer; carrying out a wet etching process to remove the first portion of the at least one oxide layer; and, dry etching the at least one nitride layer in a second dry etching process to remove the at least one nitride layer leaving a second portion of the at least one oxide layer to form an oxide offset spacer along sidewalls of the gate structure.

Abstract: Within a method for forming a topographic feature within a microelectronic substrate employed within a microelectronic fabrication, there is employed an oxidation mask layer sequentially as: (1) an oxidation mask; and then (2) an etch mask, for forming the topographic feature with a rounded corner within the microelectronic substrate. The method is particularly useful for forming within semiconductor substrates isolation trenches with rounded corners, such as to provide for enhanced performance of microelectronic devices formed within active regions adjacent the isolation trenches and isolation regions formed therein.

Abstract: A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

Abstract: A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

Abstract: A semiconductor device (1) has a fin (2) and a multiple gate electrode (3) over the fin (2), the multiple gate electrode (3) being a layer of gate electrode material with a substantially planar surface (13b) to support a patterned mask (14a), the mask (14a) having a uniform thickness and a planar surface controlling the patterning dimensions of the patterned mask (14a).

Abstract: The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.