Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-Like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method for fabricating a capacitor in an integrated circuit, using tantalum oxide as the dielectric layer to obtain a higher capacitance. A barrier layer is formed between the polysilicon layer and the tantalum oxide layer to prevent the formation of a silicon oxide layer. Thus, that capacitance of the capacitor is not reduced by the additional thickness of the silicon oxide layer.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-Like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method of fabricating a dual damascene structure is provided comprising forming a photoresist layer on a dielectric layer. A mask including a region that light completely passes over, a region that light partially passes over and a dense region is used for exposure. A development step is carried out to remove the photoresist layer under the region that light completely passes over, to partially remove the photoresist layer under the region that light partially passes over and to leave the photoresist layer under the dense region. The photoresist layer remaining from the forgoing step and the dielectric layer are partially removed to form a via and a trench in the dielectric layer. The via and the trench are filled with metal to form a dual damascene structure.

Abstract: Fabricating a semiconductor memory device with a capacitor includes forming a first insulating layer on a substrate, covering a transfer transistor, and forming a first conducting layer that penetrates the first insulating layer and is electrically coupled to one of a drain or source region of the transfer transistor. Thereafter, a pillar layer is formed at the periphery of and above the first conducting layer, and a second conducting layer is also formed on sidewalls of the pillar layer. Next, alternately a first and a second film layer are formed at least once over the first conducting layer and the second conducting layer. Then, a second insulating layer is formed above the second film layer. After that, a third conducting layer is formed and then defined such that the first, the second, and the third conducting layers, in combination with the second film layer, form a storage electrode of a charge storage capacitor.

Abstract: A process for fabricating a DRAM semiconductor memory device having a transfer transistor and a storage capacitor with a tree-shaped electrode. The tree-shaped electrode is electrically coupled to a source/drain region of the transistor. The process includes forming a first insulation layer on the device substrate covering the transfer transistor. A first electrically conductive layer is formed over and penetrating the first insulation layer such that it is electrically coupled to the source/drain region. Cylindrical structures are formed on the first conductive layer, forming a recess between the cylindrical structures. A second insulation layer covering the cylindrical structures and a portion of the exposed first electrically conductive layer is formed, with the second insulation layer covering bottom portion of the recesses incompletely. A second electrically conductive layer covering the second insulation layer and the exposed portion of the first conductive layer is formed.

Abstract: A semiconductor memory device with a tree-type capacitor having increased area for reliable storage thereon of electrical charges representative of data. The tree-type capacitor includes a storage electrode including a trunk-like conductive layer and at least a branch-like conductive layer. The trunk-like conductive layer is electrically coupled to one of the source/drain regions of a transfer transistor in the semiconductor memory device and extends substantially upright. The branch-like conductive layer has one end connected to the trunk-like conductive layer and can be structured in various shapes that allow the branch-like conductive layer to have an increased surface area. A dielectric layer is formed over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer. An overlaying conductive layer is formed over the dielectric layer and serves as an opposing electrode for the tree-type capacitor.

Abstract: Manufacturing dual-packed capacitor DRAM cells with the storage capacitors of two memory cells stacked one over the other and formed on a common trench so as to increase capacitance while decreasing area occupation by the capacitors includes forming a trench on a semiconductor substrate, forming an insulating layer above the semiconductor substrate surface covering the bottom and side walls of the trench, forming a first opening in the insulating layer exposing part of the semiconductor substrate adjacent to one side of the trench, forming a first storage electrode inside the trench above the surface of the insulating layer, which extends into the first opening and contacts the semiconductor substrate, forming a first dielectric layer above the surface of the first storage electrode, forming a common opposed electrode above the first dielectric layer which includes a vertical main section inserted into the trench, a horizontal main plate, and at least one extended section protruding vertically upward, forming

Abstract: A semiconductor memory device includes a substrate, a transfer transistor, and a storage capacitor formed on the substrate. The transfer transistor has source/drain regions, one of which is electrically connected to the storage capacitor. The storage capacitor includes a tree-like conductive layer, a dielectric layer, and an upper conductive layer. The tree-like conductive layer includes a trunk-like conductive layer and a branch-like conductive layer. The trunk-like conductive layer and the branch-like conductive layer form a storage electrode of the storage capacitor. The upper conductive layer serves as an opposing electrode of the storage capacitor.

Abstract: A semiconductor memory device such as a DRAM device with a tree-type capacitor having an increased charge storage area includes a substrate, a transfer transistor formed on the substrate and having a drain region, and the tree-type capacitor electrically connected to the drain region. The tree-type capacitor includes a storage electrode shaped in a tree-structure having a trunk-like conductive layer and at least a branch-like conductive layer branching out from the trunk-like conductive layer. A dielectric layer covers the storage electrode and an overlaying conductive layer covers the dielectric layer. The trunk-like conductive layer has one end electrically connected to the drain region of the transfer transistor. The trunk-like conductive layer and the branch-like conductive layer in combination form the storage electrode of the data storage capacitor of the semiconductor memory device and the overlaying conductive layer serves as an opposed electrode to the storage electrode.

Abstract: A method of fabricating a semiconductor memory device including a substrate with a transfer transistor formed thereon. A first insulating layer is formed on the substrate, covering the transfer transistor. A first conductive layer is formed, penetrating at least the first insulating layer and electrically coupling to a source/drain region of the transfer transistor. A second insulating layer and a stack layer are formed, and a third insulating layer is formed on the sidewalls of the stack layer. A fourth insulating layer is formed and an opening is made to expose a portion of the first conductive layer. A second conductive layer is formed over the stack layer and second insulating layer and filling the opening. The second conductive layer is defined and the stack layer and the second insulating layer below the stack layer are removed. The first and the second conductive layers are defined to form a storage electrode of the charge storage capacitor.

Abstract: A dual-packed capacitor DRAM structure includes a semiconductor substrate having a surface with a trench disposed therein, the trench having a bottom and side walls. An insulating layer covers the bottom and side walls inside the trench and covers part of the semiconductor substrate surface adjacent the trench. A pair of pass transistors are disposed symmetrically on opposite sides of the trench in the semiconductor substrate. Each pass transistor includes a gate, a source region and a drain region, the respective drain regions of the pass transistors being disposed nearest the trench. A first storage electrode is disposed above the insulating layer inside the trench and electrically coupled to the drain region of a first one of the pair of pass transistors. A first dielectric layer is disposed above a surface of the first storage electrode.

Abstract: A structure and a method to increase the capacitance of a DRAM capacitor by forming a capacitor electrode with cellular voids to add surface area. According to the method: a transfer transistor with a gate electrode and source-drain electrode regions is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, and the insulating layer is etched to form a contact void for exposing the surface of one of the source-drain electrode areas as a contact. A first conductive layer is formed on the insulating layer and is coupled to the contact through the contact void. On the first conductive layer, at least one middle insulating layer and one middle conductive layer are formed alternately to construct a multiple layer structure. Within the middle insulating layer(s), intercommunicating voids are formed through which the middle conductive layer is coupled to the first conductive layer is coupled to the first conductive layer.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: Fabricating a semiconductor memory device with a capacitor includes forming a first insulating layer on a substrate, covering a transfer transistor, and forming a first conducting layer that penetrates the first insulating layer and is electrically coupled to one of a drain or source region of the transfer transistor. Thereafter, a pillar layer is formed at the periphery of and above the first conducting layer, and a second conducting layer is also formed on sidewalls of the pillar layer. Next, alternately a first and a second film layer are formed at least once over the first conducting layer and the second conducting layer. Then, a second insulating layer is formed above the second film layer. After that, a third conducting layer is formed and then defined such that the first, the second, and the third conducting layers, in combination with the second film layer, form a storage electrode of a charge storage capacitor.

Abstract: Fabricating a semiconductor memory device on a substrate having a transfer transistor formed thereon includes forming a first insulating layer over the transfer transistor, an etching protection layer over the first insulating layer, a second insulating layer over the etching protection layer, and a stacked layer over the second insulating layer, wherein the stacked layer has a recess therein disposed above a source/drain region of the transistor and exposing a portion of the second insulating layer. A third insulating layer is formed around the periphery of the recess and a fourth insulating layer is formed to fill the recess. Then the process includes removing the third insulating layer and the fourth insulating layer from the recess, and a portion of the second insulating layer directly below the third insulating layer to form a cavity which does not expose the etching protection layer. A first conductive layer is then formed to fill the recess and the cavity, followed by removing the stacked layer.

Abstract: A semiconductor memory device includes a substrate, a transistor on the substrate, and a capacitor. The storage electrode of the capacitor includes upper and lower trunk-like conductive layers, and at least a first branch-like conductive layer. The branch-like conductive layer is L-shaped in cross section. The trunk-like conductive layer is connected to a source/drain region of the transistor.