Patents by Inventor Fang-Chun Lan

Fang-Chun Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11003282
    Abstract: A touch controller and a noise detection method that are capable of accurately detecting noises in a sensing signal are introduced. The touch controller may include a demodulator that is configured to receive a sensing signal and demodulate the sensing signal with a first frequency during a touch detection period. The demodulator may include a first filter that is configured to perform a noise detection operation on the sensing signal to output a first noise detection signal with a second frequency range adjacent to the first frequency. The first filter may have a plurality of peak frequencies different from the first frequency.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 11, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Ching Huang, Fang-Chun Lan
  • Publication number: 20210103376
    Abstract: A touch controller and a noise detection method that are capable of accurately detecting noises in a sensing signal are introduced. The touch controller may include a demodulator that is configured to receive a sensing signal and demodulate the sensing signal with a first frequency during a touch detection period. The demodulator may include a first filter that is configured to perform a noise detection operation on the sensing signal to output a first noise detection signal with a second frequency range adjacent to the first frequency. The first filter may have a plurality of peak frequencies different from the first frequency.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chun-Ching Huang, Fang-Chun Lan
  • Publication number: 20120183088
    Abstract: A lattice reduction architecture, a lattice reduction method and a detection system thereof are proposed. The proposed architecture performs lattice reduction on channel matrices corresponding to sub-carriers and includes G processing group blocks, which receives channel matrices corresponding to the sub-carriers, and each of the first to the G-1th processing group blocks includes k processing modules respectively processing k sub-carriers, and the Gth processing group block includes j processing modules, where j<=k. In each one of the processing group blocks, at least one processing module receives an initial matrix, where the processing module includes a lattice reduction processing unit provides a reduction matrix to at least one neighboring processing module when a lattice reduction algorithm is processed on a channel matrix corresponding to its respective sub-carrier for at least iteration loops according to the channel matrix and the received initial matrix.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Fu Liao, Fang-Chun Lan, Po-Lin Chiu, Yuan-Hao Huang