Abstract: A digital-to-analog conversion device is disclosed. The digital-to-analog conversion device comprises a variable delay buffer circuit and a plurality of synchronization circuits. The buffer circuit receives a digital signal with a plurality of bits and sequentially outputs a plurality of first complementary digital signal sets delayed according to the order of from MSB to LSB. Each synchronization circuit receives the first complementary digital signal set and a clock signal, uses the clock signal as the timing reference of the first complementary digital signal set, and outputs a second complementary digital signal set corresponding to the first complementary digital signal set to a digital-to-analog conversion unit, so as to convert the second complementary digital signal sets into an analog signal. The present invention uses the delays respectively corresponding to different input bits to control the timing of current switches, whereby the transient glitches are reduced.

Abstract: A digital-to-analog conversion device is disclosed. The digital-to-analog conversion device comprises a variable delay buffer circuit and a plurality of synchronization circuits. The buffer circuit receives a digital signal with a plurality of bits and sequentially outputs a plurality of first complementary digital signal sets delayed according to the order of from MSB to LSB. Each synchronization circuit receives the first complementary digital signal set and a clock signal, uses the clock signal as the timing reference of the first complementary digital signal set, and outputs a second complementary digital signal set corresponding to the first complementary digital signal set to a digital-to-analog conversion unit, so as to convert the second complementary digital signal sets into an analog signal. The present invention uses the delays respectively corresponding to different input bits to control the timing of current switches, whereby the transient glitches are reduced.