Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

Abstract: An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.

Abstract: A new and improved image sensor packaging structure and method. The image sensor packaging structure includes a glass substrate. A bond pad film, on which is provided multiple, interior flip-chip bond pads and exterior BGA (ball grid array) bond pads, is provided on the glass substrate. An inverted image sensor chip is bonded to the flip-chip bond pads on the glass substrate. The light-receiving face of the chip faces the glass substrate typically through a window provided in the bond pad film. Solder bumps are provided on the BGA bond pads on the bond pad film, and bond pads on a PCB (printed circuit board) are bonded to the respective solder bumps.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: An extended flip chip ball grid array package includes a metal heat slug bonded to the surface of a semiconductor chip. The heat slug has a bonding structure for connecting itself and a BGA substrate panel on which the semiconductor chip is mounted. The heat slug protects the chip from being damaged as well as assists heat dissipation. A first package assembly provides contact bodies on the heat slug for bonding the heat slug to contact pads formed on a BGA substrate panel. A second package assembly fixes the heat slug to a supporting structure bonded on a BGA substrate panel. Supporting stubs are formed on the supporting structure and snapped in openings formed on the contact bodies of the heat slug. Conventional packaging or testing equipment can be used for both package assemblies to manufacture or test the semiconductor chip packages.

Abstract: An enclosure is described for housing a personal computer. The natural convection system of the present invention for dissipating heat generated by the electronic components of a personal computer consists of a housing defining a cavity containing the electronic components. The major heat-producing components, such as the power supply of the computer and power transistors, are positioned at the top front of the cavity. The components are attached to a heat sink. A typical computer has a master printed circuit board. Additional printed circuit boards are plugged into the master printed circuit board. Further additional printed circuit boards may be added at any time to enhance the functionality of the computer. Therefore, plugging in additional printed circuit boards should be a simple operation. In the present invention, the master printed circuit board is attached to a side in the rear of the cavity. Other printed circuit boards are attached vertically and perpendicularly to the master printed circuit board.