Patents by Inventor Fang-Shi Lai
Fang-Shi Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8441384Abstract: A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.Type: GrantFiled: February 18, 2011Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang-Shi Lai, Manoj M. Mhala, Yung-Fu Lin, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng
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Publication number: 20120212361Abstract: A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang-Shi Lai, Manoj M. Mhala, Yung-Fu Lin, Hsu-Feng Hsueh, Chin-Hao Chang, Cheng Yen Weng
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Publication number: 20070189102Abstract: The present invention discloses a memory device with a leakage current reduction feature. The memory device includes at least one memory cell for storing a value, and at least one switch module coupled to the memory cell for generating an operating voltage at various levels depending on various operation modes of the memory cell. The operating voltage is at a first level when the memory cell is being accessed, and is at a second level lower than the first level when the memory cell is not being accessed, thereby reducing a leakage current for the memory cell.Type: ApplicationFiled: February 13, 2006Publication date: August 16, 2007Inventors: Wesley Lin, Fang-Shi Lai
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Patent number: 7183808Abstract: A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control signal and the power input terminal. That switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level. This results in the logic cell operating in standby mode. A latch circuit is coupled between the power voltage and the output terminal to preserve the voltage level of the output terminal when the logic cell operates in standby mode.Type: GrantFiled: July 26, 2004Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Fang-Shi Lai
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Patent number: 7158404Abstract: A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at a predetermined level, such that the memory cell operates in standby mode. A latch circuit is coupled between the power voltage, the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal when the memory cell operates in the standby mode.Type: GrantFiled: July 26, 2004Date of Patent: January 2, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Fang-Shi Lai
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Patent number: 7132848Abstract: A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.Type: GrantFiled: July 26, 2004Date of Patent: November 7, 2006Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.Inventor: Fang-Shi Lai
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Publication number: 20060017469Abstract: A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventor: Fang-Shi Lai
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Publication number: 20060017467Abstract: A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control signal and the power input terminal. That switch is turned off to disconnect the power voltage and the logic cell when the power control signal is at a predetermined level. This results in the logic cell operating in standby mode. A latch circuit is coupled between the power voltage and the output terminal to preserve the voltage level of the output terminal when the logic cell operates in standby mode.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventor: Fang-Shi Lai
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Publication number: 20060018146Abstract: A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at a predetermined level, such that the memory cell operates in standby mode. A latch circuit is coupled between the power voltage, the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal when the memory cell operates in the standby mode.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventor: Fang-Shi Lai
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Publication number: 20050243598Abstract: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.Type: ApplicationFiled: April 27, 2005Publication date: November 3, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny Tang, Li-Shyue Lai, Chao-Hsiung Wang, Fang-Shi Lai
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Patent number: 4943945Abstract: Threshold generator for generating half-VDD sensing potential. The threshold generator will precharge all bit lines of a memory array to 1/2-VDD prior to beginning a read of the memory array contents. First and second inverter circuits have threshold voltages selected to represent voltage limits for the bit lines. A voltage drive means is connected to the bit lines along with the inverter circuit inputs. The inverter circuit outputs enable the drive means to supply current or discharge current to and from the bit lines to maintain a voltage potential within the selected voltage limits.Type: GrantFiled: June 13, 1989Date of Patent: July 24, 1990Assignee: International Business Machines CorporationInventor: Fang-shi Lai