Patents by Inventor Fang-Tsun Chu
Fang-Tsun Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11075162Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: April 20, 2020Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20200251416Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 10629528Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: April 22, 2019Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20190252315Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 10269699Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: January 26, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 10262989Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.Type: GrantFiled: December 8, 2015Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hui Chen, Fang-Tsun Chu
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Publication number: 20180151492Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: January 26, 2018Publication date: May 31, 2018Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 9893010Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: July 20, 2016Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20160329280Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Wei-Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 9406607Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: October 21, 2013Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20160093606Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hui CHEN, Fang-Tsun CHU
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Patent number: 9245852Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.Type: GrantFiled: September 8, 2011Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Hui Chen, Fang-Tsun Chu
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Patent number: 9117677Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.Type: GrantFiled: October 13, 2011Date of Patent: August 25, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Yu Ma, Kuo-Ji Chen, Fang-Tsun Chu, Ta-Pen Guo
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Publication number: 20140042557Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 8569129Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: GrantFiled: May 31, 2011Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Publication number: 20130093052Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Yu MA, Kuo-Ji CHEN, Fang-Tsun CHU, Ta-Pen GUO
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Publication number: 20130063843Abstract: An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hui CHEN, Fang-Tsun CHU
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Publication number: 20120306023Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 8179647Abstract: An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.Type: GrantFiled: October 4, 2010Date of Patent: May 15, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fang-Tsun Chu, Kuo-Ji Chen
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Publication number: 20120081820Abstract: An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang-Tsun Chu, Kuo-Ji Chen